ZA3020 Datasheet, PDF (4/10 Pages) List of Unclassifed Manufacturers – 2A STEP DOWN PWM SWITCH MODE DC DC REGULATORS

Pin Descriptions
ZA3020
2A Step-Down, PWM, Switch-Mode
DC-DC Regulators
BS 1
IN 2
SW ₃
GND 4
8 SYNC
7 EN
6 COMP
5 FB
Pin 1: BS - Bootstrap - C5
This capacitor is needed to drive the power
switch’s gate above the supply voltage. It is
connected between SW and Bootstrap pins to
effect a floating supply across the power switch
driver. The voltage across C5 is about 5V and is
supplied by the internal +5V supply when the SW
pin voltage is low.
Pin 2: IN - Supply Voltage
The ZA3020 operates from a +4.75V to +25V
unregulated input. C1 is needed to prevent large
voltage spikes from appearing at the input.
Pin 3: SW - Switch
This connects the inductor to either IN through M1
or to GND through M2.
Pin 4: GND - Ground
This pin is the voltage reference for the regulated
voltage. For this reason care must be taken in its
layout. This node should be placed outside of the
D_SCH to C1 ground path to prevent switching
current spikes to induce voltage noise into the
part.
Pin 5: FB - Feedback
An external resistor divider from the output voltage
to GND, tapped to the FB pin sets the output
voltage. To prevent current limit run away during
a short circuit fault condition the frequency fold
back comparator lowers the oscillation frequency
when the FB voltage is below 650mV.
Pin 6: COMP - Compensation
This node is the output of the transconductance
error amplifier and the input to the current
comparator. Frequency compensation is done at
this node by connecting a series R-C to ground.
See the compensation section for exact details.
Pin 7: EN - Enable/UVLO
A voltage greater than 2.495V enables operation.
Leave the input unconnected if unused. An Under
Voltage Lockout (UVLO) function can be
implemented by the addition of a resistor divider
from V_IN to GND. For complete low current
shutdown its needs to be less than 0.7V.
Pin 8: SYNC - Synchronization Input
This pin is used to synchronize the internal
oscillator frequency to an external source. There
is an internal 11Kȍ pull down resistor to GND
hence leave the input unconnected if unused.
Sync Pin Operation
The SYNC pin driving waveform should be a
square wave with a rise time of less than 20ns.
Minimum Hi voltage level is 2.7V. Low level is
less than 0.8V. The frequency of the external Sync
signal needs to be greater than 445 KHz.
A rising edge on the SYNC pin forces a reset of
the oscillator. The upper DMOS is switched off
immediately if it is not already off. 250nS later the
upper DMOS turns on connecting SW to V_IN.
ZA3020 Rev. 3.5 2003-04-22
www.vimicro.com
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