STC62WV1024 Datasheet, PDF (4/10 Pages) List of Unclassifed Manufacturers – VERY LOW POWER VOLTAGE CMOS SRAM

STC
„AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
Output Load
0.5Vcc
CL = 30pF+1TTL
CL = 100pF+1TTL
STC62WV1024
„ KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
,
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
„ AC ELECTRICAL CHARACTERISTICS ( TA = -40^oC to + 85^oC )
READ CYCLE
JEDEC
PARAMETER
NAME
t _AVAX
t _AVQV
t _E1LQV
t _E2HOV
t _GLQV
t _E1LQX
t _E2HOX
t _GLQX
t _E1HQZ
t _E2HQZ
t _GHQZ
t _AXOX
PARAMETER
NAME
DESCRIPTION
t_RC
t_AA
t_ACS1
t_ACS2
t_OE
t_CLZ1
t_CLZ2
t_OLZ
t_CHZ1
t_CHZ2
t_OHZ
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
tOH
Data Hold from Address Change
(CE1)
(CE2)
(CE1)
(CE2)
(CE1)
(CE2)
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
55 -- --
-- -- 55
-- -- 55
-- -- 55
-- -- 30
10 -- --
10 -- --
10 -- --
-- -- 35
-- -- 35
-- -- 30
10 -- --
CYCLE TIME : 70ns
(Vcc = 2.7~5.5V)
MIN. TYP. MAX.
70 -- --
-- -- 70
-- -- 70
-- -- 70
-- -- 40
10 -- --
10 -- --
10 -- --
-- -- 40
-- -- 40
-- -- 35
10 -- --
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STC62WV1024
4
Revision 2.1
Jan. 2004