MRD510B Datasheet, PDF (4/8 Pages) List of Unclassifed Manufacturers – Single Channel F2F Decoder IC

Uniform Industrial Corp.
MRD510B
Single Channel F2F Decoder IC
4. PIN DESCRIPTION
1 GND
2 SEN1N
3 SEN1P
4 OP1OUT
5 OP2NIN
6 OP2OUT
7 OP3OUT
8 VREFIN
9 VDD
10 NC
11 VDD
12 OSCI
13 OSCO
14 IBS
15 OCK
16 OUTX
17 OUT
18 CLS
19 ADJ
20 RES
Input from magnetic head
Input from magnetic head
Amplifier OP1 output
Amplifier OP2 - input
Amplifier OP2 output
Amplifier OP3 output
Reference voltage for analog signal processing
RC oscillator input
RC oscillator output
Select ignore leading bit, “LOW” for 4 bits and “HIGH” for 8 bits
Negative read out clock for F2F channel 1
Negative read out data for F2F channel 1
Positive read out data for F2F channel
Card Loading Signal output, “LOW” after ignore bits,
“HIGH” if no input for around 12.5mS
Adjust read out clock pulse width for F2F channel 1
Power on reset, LOW reset the logic circuit and enter idle mode.
Approx. 10mS after HIGH level to normal function
5. FUNCTION DESCRIPTION
Data signal inputs read from a magnetic card via a magnetic head are fed into the SEN1P
and SEN1N pins, amplified and wave shaped by internal analog circuitry, then converted to
logic level F2F data format. Once the F2F signals are detected, the decoding logic
ignores the leading 4 or 8 bits (set by IBS pin), via the ignored bits the reference bit length
is determined. The succeeding inputs are identified as bit 0 or 1 by the average bit length
of preceding two bits, if the data toggles before 70% of the reference bit length then the
data is identified as a “1” bit and the next data toggle regarded as the beginning of next
data bit. If the data toggles after 70% of the reference bit length then the data is identified
as a “0” bit and the current data toggle is as the beginning of next data.
After the ignored bits, then pin CLS will be pulled low, the succeeding data bit will be shifted
out after the beginning of next data bit.
The pin OCK will be pulled low after the next data is detected and a 12uS delay inserted, it
will be kept low for 14 to 60uS depending on the external resistor connected to pin ADJ. If
the next bit comes before OCK goes high, then OCK1 (OCK2) will be forced to pull high
and then begins next cycle, it means that the data signals will be ready before OCK goes
low and stay valid till 12uS before next down edge of OCK.
Page : ₂
October, 1997