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MA2909 Datasheet, PDF (4/13 Pages) List of Unclassifed Manufacturers – RADIATION HARD MICROPROGRAM SEQUENCER
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MA2909/11
Cycle S1 S0 FE PUP µPC REG STK0 STK1 STK2 STK3 YOUT
Comment
Principal Use
N LLLL
N+1
-
N LLLH
N+1
-
N L L HX
N+1
-
N L HL L
N+1
-
N L HL H
N+1
-
N L HHX
N+1
-
N HL L L
N+1
-
N HL L H
N+1
-
N HL HX
N+1
-
N HHL L
N+1
-
N HHL H
N+1
-
N HHHX
N+1
-
J
K
J+1 K
J
K
J+1 K
J
K
J+1 K
J
K
K+1 K
J
K
K+1 K
J
K
K+1 K
J
K
Ra + 1 K
J
K
Ra + 1 K
J
K
Ra + 1 K
J
K
D+1 K
J
K
D+1 K
J
K
D+1 K
Ra
Rb
Rc
Rd
J
Pop Stack
End Loop
Rb
Rc
Rd
Ra
-
Ra
Rb
Rc
Rd
J
Push µPC
Set-up Loop
J
Ra
Rb
Rc
-
Ra
Rb
Rc
Rd
J
Continue
Continue
Ra
Rb
Rc
Rd
-
Ra
Rb
Rc
Rd
K
Pop Stack;
End Loop
Rb
Rc
Rd
Ra
-
Use AR for Address
Ra
Rb
Rc
Rd
K
Push µPC;
JSR AR
J
Ra
Rb
Rc
- Jump to Address in AR
Ra Rb Rc Rd K Jump to Address in AR JMP AR
Ra
Rb
Rc
Rd
-
Ra
Rb
Rc
Rd Ra
Rb
Rc
Rd
Ra
-
Jump to Address in
STK0; Pop Stack
RTS
Ra
Rb
Rc
Rd Ra
J
Ra
Rb
Rc
-
Ra
Rb
Rc
Rd
Ra
Ra
Rb
Rc
Rd
-
Ra
Rb
Rc
Rd
D
Jump to Address in
STK0; Push µPC
Jump to Address in
STK0
Pop Stack;
Stack Ref
(Loop)
End Loop
Rb
Rc
Rd
Ra
-
Jump to Address on D
Ra Rb Rc Rd D Jump to Address on D;
J
Ra
Rb
Rc
-
Push µPC
Ra Rb Rc Rd D Jump to Address on D
Ra
Rb
Rc
Rd
-
JSR D
JMP D
1 = High, 0 = Low, X = Irrelevant, Assume Cn = High
Note: STK0 is the location addressed by the stack pointer
Table 2: Output and Internal Next-Cycle Register States for 2909/2911
Table 3 (Page 5) illustrates the execution of a subroutine
using the 2909. The configuration of Figure 2 is assumed. The
instruction being executed at any given time is the one
contained in the microword register (µWR). The contents of the
µWR also control (indirectly, perhaps) the four signals S0, S1,
FE, and PUP. The starting address of the subroutine is applied
to the D inputs of the 2909 at the appropriate time.
In the column on the left is the sequence of
microinstructions to be executed. At address J+2, the
sequence control portion of the microinstruction contains the
command “Jump to subroutine at A”.
At the time T2, this instruction is in the µWR, and the 2909
inputs are set-up to execute the jump and save the return
address. The subroutine address A is applied to the D inputs
from the µWR and appears on the Y outputs. The first
instruction of the subroutine, I(A), is accessed and is at the
inputs of the µWR. On the next clock transition, l(A) is loaded
into the µWR for execution, and the return address J + 3 is
pushed on to the stack. The return instruction is executed at
T5. Table 4 is a similar timing chart showing one subroutine
linking to a second, the latter consisting of only one
microinstruction.
4
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