DPL4519 Datasheet, PDF (4/64 Pages) List of Unclassifed Manufacturers – Sound Processor for Digital and Analog Surround Systems

DPL 4519G
PRELIMINARY DATA SHEET
Sound Processor for Digital and Analog Surround
Systems
The hardware and software description in this docu-
ment is valid for the DPL 4519G version A1 and follow-
ing versions.
1. Introduction
The DPL 4519G processor is designed as part of the
Micronas chip set for digital and analog Surround Sys-
tems i. e. Dolby Digital, MPEG 2 Audio, or Dolby Pro-
Logic. The combination of MAS 3528E, DPL 4519G,
and MSP 44x0G is a complete 5.1 channel Dolby Digi-
tal decoder and playback solution, while DPL 4519G
and MSP 44x0G alone, represent a complete Dolby
Surround Pro Logic system.
The DPL 4519G receives its incoming data via highly
flexible I²S interfaces. The three I²S input interfaces
can be configured as three asynchronous I²S inputs or
two synchronous and one asynchronous interface. In
the latter case, the asynchronous interface allows
reception of 2-8 channels with arbitrary sample rate
ranging from 8 to 48 kHz. The synchronization is per-
formed by means of an adaptive high-quality sample
rate converter.
In an application together with the Dolby Digital
decoder MAS 3528E, eight channels (left, right, sur-
round left, surround right, center, subwoofer, Pro Logic
encoded left, Pro Logic encoded right) are fed in and
processed in the DPL 4519G.
Similar to the multichannel I²S input interface, the DPL
is provided with an 8-channel I²S output interface,
which can be connected to a MSP 44x0G. Therefore
all 8 channels can be routed to each output in both
ICs.
The baseband processing including e.g. balance,
bass, treble, and loudness is performed at a fixed sam-
ple rate of 48 kHz.
Fig. 1–1 shows a simplified functional block diagram of
the DPL 4519G.
The DPL 4519G is pin-compatible to members of the
MSP 34xx family. This speeds up PCB development
for customers using MSPs.
The software interface of the DPL 4519G is also
largely the same as for members of the MSP family.
The ICs are produced in submicron CMOS technology
and are available in PQFP80, PLQFP64 and in
PSDIP64 packages.
I²S1
I²S2
I²S3
I²S
I²S
I²S
(2..8-channel)
SCART1
SCART2
SCART3
SCART4
MONO
ProLogic
processing
Fig. 1–1: Simplified block diagram of the DPL 4519G
4
Main
Sound
Processing
AUX
Sound
Processing
DAC
DAC
DAC
SCART
Output
Select
Main
Subwoofer
AUX
I²S
(8-channel)
SCART1
SCART2
Micronas