AKD5381 Datasheet, PDF (4/21 Pages) List of Unclassifed Manufacturers – Evaluation board Rev.A for AK5381

ASAHI KASEI
[AKD5381]
„ DIP Switch set up
[SW2] (MODE1): Setting the evaluation mode for AK5381 and AK4103
ON is “H”, OFF is “L”.
No.
Name
1
DIF
OFF (“L”)
MSB justified
ON (“H”)
I²S Compatible
2
CKS2
3
CKS1
See Table 2
4
CKS0
5
DIT1
6
DIT0
See Table 3
Table 1. Mode Setting
CKS2
L
L
L
L
H
H
H
H
CKS1
L
L
H
H
L
L
H
H
CKS0
L
H
L
H
L
H
L
H
Input Level HPF Master/Slave
MCLK
CMOS
ON
Slave
256/384/512/768fs
CMOS OFF
Slave
256/384/512/768fs
CMOS
ON
CMOS
ON
Master
Master
256fs (∼ 96kHz)
512fs (∼ 48kHz)
TTL
ON
Slave
256/384/512/768fs
CMOS
ON
CMOS
ON
Reserved
Master
384fs (∼ 96kHz)
Master
768fs (∼ 48kHz)
Table 2. Mode Setting of AK5381
SCLK
≥ 48fs or 32fs
≥ 48fs or 32fs
64fs
64fs
≥ 48fs or 32fs
64fs
64fs
Mode
0
1
2
3
DIT1
DIT0
MCLK
fs
OFF
OFF
256fs
∼ 96kHz
OFF
ON
N/A
N/A
ON
OFF
512fs
∼ 48kHz
ON
ON
384fs
∼ 48kHz
Table 3. MCLK Frequency Setting of AK4103
Default
Note: AK4103 does not support MCLK=768fs.
„ The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Resets the AK5381 and AK4103. Keep “H” during normal operation.
<KM069200>
-4-
2002/06