RTL8139C Datasheet, PDF(38/62 Page) List of Unclassifed Manufacturers – REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT

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RTL8139C Datasheet, PDF (38/62 Pages) List of Unclassifed Manufacturers – REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT

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RTL8139C(L)

Bit

15-10

Symbol

FBTBEN

SERREN

ADSTEP

PERRSP

VGASNOO

MWIEN

SCYCEN

BMEN

MEMEN

IOEN

Description

Reserved

Fast Back-To-Back Enable: Config3<FBtBEn>=0:Read as 0. Write operation has no effect. The

RTL8139C(L) will not generate Fast Back-to-back cycles. When Config3<FbtBEn>=1, This read/write

bit controls whether or not a master can do fast back-to-back transactions to different devices.

Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means the

master is allowed to generate fast back-to-back transaction to different agents. A value of 0 means fast

back-to-back transactions are only allowed to the same agent. This bitâs state after RST# is 0.

System Error Enable: When set to 1, the RTL8139C(L) asserts the SERRB pin when it detects a parity

error on the address phase (AD<31:0> and CBEB<3:0> ).

Address/Data Stepping: Read as 0, write operation has no effect. The RTL8139C(L) never performs

address/data stepping.

Parity Error Response: When set to 1, RTL8139C(L) will assert the PERRB pin on the detection of a

data parity error when acting as the target, and will sample the PERRB pin as the master. When set to 0,

any detected parity error is ignored and the RTL8139C(L) continues normal operation.

Parity checking is disabled after hardware reset (RSTB).

VGA palette SNOOP: Read as 0, write operation has no effect.

Memory Write and Invalidate cycle Enable: Read as 0, write operation has no effect.

Special Cycle Enable: Read as 0, write operation has no effect. The RTL8139C(L) ignores all special

cycle operation.

Bus Master Enable: When set to 1, the RTL8139C(L) is capable of acting as a bus master. When set to

0, it is prohibited from acting as a PCI bus master.

For the normal operation, this bit must be set by the system BIOS.

Memory Space Access: When set to 1, the RTL8139C(L) responds to memory space accesses. When

set to 0, the RTL8139C(L) ignores memory space accesses.

I/O Space Access: When set to 1, the RTL8139C(L) responds to IO space access. When set to 0, the

RTL8139C(L) ignores I/O space accesses.

Status: The status register is a 16-bit register used to record status information for PCI bus related events. Reads to this register

behave normally. Writes are slightly different in that bits can be reset, but not set.

2002/01/10

Rev.1.4

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