IP1001LF Datasheet, PDF (38/48 Pages) List of Unclassifed Manufacturers – Integrated 10/100/1000 Gigabit Ethernet Transceiver

4.13 PHY Specific Control & Status Register (Reg16)
IP1001 LF
Data Sheet
Bit
16.0
16.1
16.2
16[4:3]
16[6:5]
16[8:7]
Name
Description
RXPHASE_SEL
This bit is used to adjust RX clock phase at
GMII/ RGMII interface
0: No intentional delay is added on RX_CLK
1: An intentional delay is added on RX_CLK
(about 2ns delay in 1000BASE-T, and about
4ns delay in 100BASE-TX and 10BASE-T).
(Pin 48 sets the default value of this bit)
TXPHASE_SEL
This bit is used to adjust TX clock phase at
GMII/ RGMII interface
0: No intentional delay is added on
GTX_CLK/ TXC
1: An intentional delay is added on
GTX_CLK/ TXC
(about 2ns delay in 1000BASE-T, and about
4ns delay in 100BASE-TX and 10BASE-T)
Pin 49 sets the default value of this bit.
Repeater Mode 1 = Enable repeater mode
0 = Disable repeater mode
Reserved
RXCLK_DRIVE[1:0] These 2 bits are used to adjust driving
current of RX_CLK.
I/F
2’b00 2’b01 2’b10 2’b11
MII
2mA 4mA 8mA 2mA
GMII/
RGMII 2mA 4mA 8mA 2mA
(10/100)
GMII/
RGMII 4mA 8mA 12mA 2mA
(1000)
RXD_DRIVE[1:0] These 2 bits are used to adjust driving
current of RXD[7:0], RX_ER, and RX_DV.
Type
RW
RW
RW
RW
RW
HW
Reset
Pin 48
Pin 49
0
01
10
10
SW
Reset
NA
NA
NA
NA
NA
NA
The driving current of RXD[3:0] and RX_DV
I/F
2’b00 2’b01 2’b10 2’b11
MII
2mA 4mA 8mA 2mA
GMII/
RGMII 2mA 4mA 8mA 2mA
(10/100)
GMII/
RGMII 4mA 8mA 12mA 2mA
(1000)
16.9
Jabber
The driving current of RXD[7:4] and RX_ER
I/F
2’b00 2’b01 2’b10 2’b11
MII
2mA 4mA 8mA 2mA
GMII 2mA 4mA 8mA 2mA
(10/100)
GMII 4mA 8mA 12mA 2mA
(1000)
RGMII 2mA 2mA 2mA 2mA
(10/100)
RGMII 4mA 2mA 12mA 2mA
(1000)
1 = Enable Jabber
RW 1
NA
Copyright © 2006, IC Plus Corp.
38/48
Dec. 18, 2007
IP1001-DS-R06