LM3S2110 Datasheet, PDF (361/485 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S2110 Microcontroller
Register 1: CAN Control (CANCTL), offset 0x000
This control register initializes the module and enables test mode and interrupts.
The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting
or resetting INIT. If the device goes bus-off, it sets INIT, stopping all bus activities. Once INIT
has been cleared by the CPU, the device then waits for 129 occurrences of Bus Idle (129 * 11
consecutive High bits) before resuming normal operations. At the end of the bus-off recovery
sequence, the Error Management Counters are reset.
During the waiting time after INIT is reset, each time a sequence of 11 High bits has been monitored,
a Bit0Error code is written to the CANSTS status register, enabling the CPU to readily check
whether the CAN bus is stuck at dominant or continuously disturbed and to monitor the proceeding
of the bus-off recovery sequence.
CAN Control (CANCTL)
CAN0 base: 0x4004.0000
Offset 0x000
Type R/W, reset 0x0000.0001
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
Test
CCE
DAR reserved EIE
SIE
IE
INIT
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit/Field
31:8
7
6
5
4
3
Name
reserved
Test
CCE
DAR
reserved
EIE
Type
RO
R/W
R/W
R/W
RO
R/W
Reset
0x0000
0
0
0
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Test Mode Enable
0: Normal Operation
1: Test Mode
Configuration Change Enable
0: Do not allow write access to the CANBIT register.
1: Allow write access to the CANBIT register if the INIT bit is 1.
Disable Automatic Retransmission
0: Auto retransmission of disturbed messages is enabled.
1: Auto retransmission is disabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Error Interrupt Enable
0: Disabled. No Error Status interrupt is generated.
1: Enabled. A change in the Boff or EWarn bits in the CANSTS register
generates an interrupt.
November 29, 2007
361
Preliminary