TMS320C6000 Datasheet, PDF (36/45 Pages) Texas Instruments – Code Composer Studio Tutorial

ASRAM
< 10 MHz
SYNCHRONOUS SRAMs
EMIF Case Study
ASRAM
< 100 MHz
< 166 MHz
Pipelined
SBRAM
Flow thru
SBRAM
< 133 MHz
Double
Data Rate
< 200 MHz
<400 MHz Data
Late Write
< 300 MHz
ZBT
< 166 MHz
Not compatible
C6000 Compatible
Next Generation
Not Planned
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
71
SYNCHRONOUS SRAMs
Asynchronous SRAMs present long critical path...
Control
Memory
Data
Address
Array
…and then a high access time
Control
Read
Fast
Address
ASRAM
Data
A1
A2
tacc = 10 ns
tacc = 10 ns
D1
D2
Control1
Read
Slow Address1
ASRAM
Data1
A1
tacc = 100 ns
D1
Ingeniería Electrónica
Sistemas Electrónicos Digitales Avanzados
72