CH7013B Datasheet, PDF (34/46 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder

CHRONTEL
CH7013B
The PLL N value register determines the division factor applied to the VCO output before being applied to the PLL phase
detector, when the CH7013B is operating in master or pseudo-master mode. In slave mode, the value of ‘N’ is always 1.
This register contains the lower 8 bits of the complete 10-bit N value. The pixel clock generated in a master and pseudo-
master modes is calculated according to the equation below:
Fpixel = Fref* [(N+2) / (M+2)]
When using a 14.318 MHz frequency reference, the required M and N values for each mode are shown in the table
below.
Table 25. M and N Values for Each Mode
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VGA Resolution, TV
Standard, Scaling Ratio
512x384, PAL, 5:4
512x384, PAL, 1:1
512X384, NTSC, 5:4
512X384, NTSC, 1:1
720X400, PAL, 5:4
720X400, PAL, 1:1
720X400, NTSC, 5:4
720X400, NTSC, 1:1
640X400, PAL, 5:4
640X400, PAL, 1:1
640X400, NTSC, 5:4
640x400, NTSC, 1:1
640X400, NTSC, 7:8
640X480, PAL, 5:4
640X480, PAL, 1:1
N 10-
bits
20
9
126
110
53
339
106
70
108
9
94
22
190
20
9
M 9-
bits
13
4
89
63
26
138
63
33
61
3
63
11
89
13
4
Mode
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VGA Resolution, TV
Standard, Scaling Ratio
640X480, PAL, 5:6
640X480, NTSC, 1:1
640X480, NTSC, 7:8
640X480, NTSC, 5:6
800X600, PAL, 1:1
800X600, PAL, 5:6
800X600, PAL, 3:4
800X600, NTSC, 5:6
800X600, NTSC, 3:4
800X600, NTSC, 7:10
720X576, PAL, 1:1
720X480, NTSC, 1:1
800X500, PAL, 1:1
640X400, NTSC, 1:1
N 10-
bits
9
110
126
190
647
86
284
94
62
302
31
31
242
2
M 9-
bits
3
63
63
89
313
33
103
33
19
89
33
33
197
2
Buffered Clock Output Register
Symbol: BCO
Address: 17h
Bits: 6
Bit:
Symbol:
Type:
Default:
7
Reserved
R/W
0
6
Reserved
R/W
1
5
SHF2
R/W
0
4
SHF1
R/W
0
3
SHF0
R/W
0
2
SCO2
R/W
0
1
SCO1
R/W
0
0
SCO0
R/W
0
The buffered clock output register determines which clock is selected to be output at the buffered clcok output pin,
and what frequency value should be output if a VCO derived signal is output. The tables below show the possible
outputs signals.
Table 26.Clock Output Selection
SCO[2:0]
000
001
010
011
100
101
110
111
Buffered Clock Output
14MHz crystal
(for test use only)
VCO divided by K3 (see Table 27)
Field ID signal
(for test use only)
(for test use only)
TV horizontal sync (for test use only)
TV vertical sync (for test use only)
34
201-0000-069 Rev. 1.2, 9/1/2004