INT5130 Datasheet, PDF (33/38 Pages) List of Unclassifed Manufacturers – Integrated Powerline MAC/PHY Transceiver

INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
Parameter
Symbol
Parameter Name
Test Condition Min
t_{JTAG_F}
TCK Frequency
t_{JTAG_P}
TCK Period
100
t_{JTAG_H}
TCK High Time
@ 2.0V
45
t_{JTAG_L}
TCK Low Time
@ 0.8V
45
t_{JTAG_R}
TCK Rise Time
t_{JTAG_FT}
TCK Fall Time
t_{JTAG_SU}
TDI, TMS Setup Time
8
t_{JTAG_H}
TDI, TMS Hold Time
10
t_{JTAG_VD}
TDO Valid Delay
3
t_{JTAG_FD}
TDO Float Delay
t_{JTAG_OVD} All Outputs (Non-Test) Valid Delay
3
t_{JTAG_OFD} All Outputs (Non-Test) Float Delay
t_{JTAG_ISU}
All Inputs (Non-Test) Setup Time
8
t_{JTAG_IH}
All Inputs (Non-Test) Hold Time
7
Table 15: JTAG (IEEE 1149.1) DC Characteristics
Max
10
4
4
30
50
25
36
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INTELLON CONFIDENTIAL
33
Rev 8.1
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