LM3S815 Datasheet, PDF (325/423 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S815 Data Sheet
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004
This register accesses four control bits when written, and accesses seven status bits when read.
The status register consists of seven bits, which when read determine the state of the I²C bus
controller.
The control register consists of four bits: the RUN, START, STOP, and ACK bits.
The START bit causes the generation of the START, or REPEATED START condition.
The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst.
To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with
the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1),
STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is
completed (or aborted due an error), the interrupt pin becomes active and the data may be read
from the I2CMDR register. When the I²C module operates in Master receiver mode, the ACK bit
must be set normally to logic 1. This causes the I²C bus controller to send an acknowledge
automatically after each byte. This bit must be reset when the I²C bus controller requires no further
data to be sent from the slave transmitter.
I2C Master Status (I2CMCS): Read
Offset 0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
BUSBSY IDLE ARBLST DATACK ADRACK ERROR BUSY
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I2C Master Control (I2CMCS): Write
Offset 0x004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
ACK STOP START RUN
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
WO
WO
WO
WO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
Name
Read-Only Status Register
31:7
reserved
Type
RO
6
BUSBSY
R
5
IDLE
R
Reset Description
0
Reserved bits return an indeterminate value, and should never
be changed.
0
This bit specifies the state of the I²C bus. If set, the bus is busy;
otherwise, the bus is idle. The bit changes based on the START
and STOP conditions.
0
This bit specifies the I²C controller state. If set, the controller is
idle; otherwise the controller is not idle.
April 28, 2007
325
Preliminary