LM3S801 Datasheet, PDF (315/397 Pages) List of Unclassifed Manufacturers – Microcontroller

LM3S801 Data Sheet
Register 8: Analog Comparator Control 0 (ACCTL0), offset 0x24
Register 9: Analog Comparator Control 1 (ACCTL1), offset 0x44
Register 10: Analog Comparator Control 2 (ACCTL2), offset 0x64
These registers configure that comparator’s input and output.
Analog Comparator Control 0 (ACCTL0)
Offset 0x024
31
30
29
28
27
26
25
Type
RO
Reset
0
15
Type
RO
Reset
0
RO
RO
RO
0
0
0
14
13
12
reserved
RO
RO
RO
0
0
0
RO
RO
RO
0
0
0
11
10
9
ASRCP
RO
RR/OW
RR/OW
0
0
0
24
23
22
reserved
RO
RO
RO
0
0
0
8
7
6
reserved
RO
RO
RO
0
0
0
21
20
19
18
RO
RO
RO
RO
0
0
0
0
5
4
3
2
ISLVAL
ISEN
RO
RR/OW
RR/OW
RR/OW
0
0
0
0
17
16
RO
RO
0
0
1
0
CINV
RR/OW
0
reserved
RROO
0
Bit/Field
31:11
10:9
Name
reserved
ASRCP
8:5
reserved
4
ISLVAL
3:2
ISEN
Type
RO
R/W
RO
R/W
R/W
Reset
0
0
Description
Reserved bits return an indeterminate value, and should
never be changed.
The ASRCP field specifies the source of input voltage to the
VIN+ terminal of the comparator. The encodings for this field
are as follows:
ASRCP Function
00
Pin value
01
Pin value of C0+
10
Internal voltage reference
11
Reserved
0
Reserved bits return an indeterminate value, and should
never be changed.
0
The ISLVAL bit specifies the sense value of the input that
generates an interrupt if in Level Sense mode. If 0, an
interrupt is generated if the comparator output is Low.
Otherwise, an interrupt is generated if the comparator output
is High.
0
The ISEN field specifies the sense of the comparator output
that generates an interrupt. The sense conditioning is as
follows:
ISEN Function
00
Level sense, see ISLVAL
01
Falling edge
10
Rising edge
11
Either edge
October 8, 2006
315
Preliminary