HD49801FB Datasheet, PDF (31/43 Pages) List of Unclassifed Manufacturers – Digital Signal Processing IC for CCD Cameras

HD49801FB
HD49801FB
• Definition of H.REF
H.REF is the standard for determining:
— Memory R/W start/stop timing
— BF, CBLK, CSYNC pulse timing
• Conditions required of H.REF
— H.REF is a pulse generated from the sensor clock (fs), and must be phase stable with respect to fs.
— It must be a continuous pulse with no missing pulse periods during the BLK or other period.
— Synchronization is horizontal scan synchronization.
— t_WH = Min 2 fs^–1
— Timing corresponding to the effective pixel region for the falling edge of HREFI.
Min
t_F
30 fs^–1
t_B
0
However, there are no special requirements when the following relationship is met: fs = 4n · f_H
(where n is an integer).
— Setting example for H synchronization pulses (for an NTSC 270,000 pixel CCD)
Name
H synchronization pulse 1
H synchronization pulse 2
H synchronization pulse 3
H synchronization pulse 4
H synchronization pulse 5
H synchronization pulse 6
H synchronization pulse 7
H synchronization pulse 8
H synchronization pulse 9
Symbol D10
D1
H1
10 0001 1011
H2
00 1110 1100
H3
0001 0110
H4
0010 1110
H5
0100 0011
H6
0101 1010
H7
0101 1111
H8
0111 1000
H9
1000 1011
Notes
539 ^{Values with respect to the falling edge of}
HREFI.
236
22 ^{Values with respect to H synchronization}
46 ^{pulses 1 and 2.}
67
90
95
120
138
• When a 410,000 pixel CCD is used, the following timings, which are related to the sensor clock and the
sensor specifications, change.
— Memory R/W start/stop addresses
— BF, CBLK, CSYNC pulse timings
— Iris state data A13, H count 1 to 6
31