USBMOD4 Datasheet, PDF (3/12 Pages) List of Unclassifed Manufacturers – USB Plug and Play Parallel 8-Bit FIFO Development Module (Second Generation)

designated as the TEST pin and should
be tied to GND for normal operation.
• Integrated Level Converter on FIFO
interface and control signals
The previous devices would drive the
FIFO and control signals at 5v CMOS
logic levels. The new device has a
separate VCC-IO (VIO on the module)
pin allowing the device to directly
interface to 3.3v and other logic families
without the need for external level
converter I.C.'s
• Power Management control for USB
Bus Powered, high current devices
A new PWREN# signal (/PEN on the
module) which can be used to directly
drive a transistor or P-Channel MOSFET
in applications where power switching of
external circuitry is required. A new
EEPROM based option makes the device
pull gently down its FIFO interface lines
when the power is shut off (PWREN# is
High). In this mode, any residual voltage
on external circuitry is bled to GND
when power is removed thus ensuring
that external circuitry controlled by
PWREN# resets reliably when power is
restored. PWREN# can also be used be
external circuitry to determine when
USB is in suspend mode (PWREN# goes
high).
• Lower Suspend Current
Integration of RCCLK within the device
and internal design improvements reduce
the suspend current of the FT245BM to
under 200uA (excluding the 1.5k pull-up
on USBDP) in USB suspend mode. This
allows greater margin for peripherals to
meet the USB Suspend current limit of
500uA.
• Support for USB Isocronous
Transfers
Whilst USB Bulk transfer is usually the
best choice for data transfer, the
scheduling time of the data is not
guaranteed. For applications where
scheduling latency takes priority over
USBMOD4 Datasheet
data integrity such as transferring audio
and low bandwidth video data, the new
device now offers an option of USB
Isocronous transfer via an option bit in
the EEPROM.
• Programmable FIFO TX Buffer
Timeout
In the previous device, the TX buffer
timeout used to flush remaining data
from the receive buffer was fixed at
16ms timeout. This timeout is now
programmable over USB in 1ms
increments from 1ms to 255ms thus
allowing the device to be better
optimised for protocols requiring faster
response times from short data packets.
• Send Immediate / Wakeup (SI/WU)
signal
The new Send Immediate / WakeUp
signal combines the two functions on a
single pin. If USB is in suspend mode
(and remote wakeup is enabled in the
EEPROM), strobing this pin low will
cause the device to request a resume
from suspend (WakeUp) on the USB
Bus. Normally, this can be used to wake
up the Host PC. During normal
operation, if this pin is strobed low any
data in the device RX buffer will be sent
out over USB on the next Bulk-IN
request from the drivers regardless of the
packet size. This can be used to optimize
USB transfer speed for some
applications.
• Relaxed VCC Decoupling
The 2nd generation devices now
incorporate a level of on-chip VCC
decoupling. Though this does not
eliminate the need for external
decoupling capacitors, it significantly
improves the ease of PCB design
requirements to meet FCC, CE and other
EMI related specifications.
• Bit Bang Mode
The 2nd generation device has a new
option referred to as “Bit Bang ” mode.
In Bit Bang mode, the eight FIFO data
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