GS816118 Datasheet, PDF (3/36 Pages) List of Unclassifed Manufacturers – 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs

TQFP Pin Description
Symbol
A0, A1
A
DQA
DQB
DQC
DQD
NC
BW
BA, BB, BC, BD
CK
GW
E1
G
ADV
ADSP, ADSC
ZZ
TMS
TDI
TDO
TCK
FT
LBO
V_DD
V_SS
V_DDQ
Type
I
I
I/O
—
I
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
I
GS816118(T/D)/GS816132(D)/GS816136(T/D)
Description
Address field LSBs and Address Counter preset Inputs
Address Input
Data Input and Output pins
No Connect
Byte Write—Writes all enabled bytes; active low
Byte Write Enable for DQA, DQB Data I/Os; active low
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Output Enable; active low
Burst address counter advance enable; active low
Address Strobe (Processor, Cache Controller); active low
Sleep Mode control; active high
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
Flow Through or Pipeline mode; active low
Linear Burst Order mode; active low
Core power supply
I/O and Core Ground
Output driver power supply
Rev: 2.13 11/2004
4/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology