ES3883 Datasheet, PDF (3/4 Pages) List of Unclassifed Manufacturers – Video CD Companion Chip Product Brief

ES3883 PRODUCT BRIEF
Table 1 Visba ES3883 Pin Description (Continued)
Name
Number
I/O Definition
AUX14
39
I/O Servo SCOR (S0S1), interrupt input, or general-purpose I/O.
AUX15
40
I/O Interrupt input or general-purpose I/O.
DSC_D[7:0]
81,83,85,93,95,97,99,8 I/O Data for programming to access internal registers.
DSC_S
10
I Strobe for programming to access internal registers.
DCLK
EXT_CLK
O Dual-purpose. DCLK is the MPEG decoder clock.
12
I EXT_CLK is the external clock. EXT_CLK is an input during bypass PLL mode.
RESET_B
13
I Video reset (active-low).
MUTE
15
O Audio mute.
MCLK
17
I Audio master clock.
TWS
SPLL_OUT
19
I Dual-purpose. TWS is the transmit audio frame sync.
O SPLL_OUT is the select PLL output.
TSD
21
I Transmit audio data input.
TBCK
22
I Transmit audio bit clock.
RWS
O Dual-purpose. RWS is the receive audio frame sync.
SEL_PLL1
I SEL_PLL[1:0] select the PLL clock frequency for the DCLK output.
SEL_PLL1 SEL_PLL0 DCLK
23
0
0
Bypass PLL (input mode)
0
1
27 MHz (output mode)
1
0
32.4 MHz (output mode)
1
1
40.5 MHz (output mode)
RSTOUT_B
NC
RSD
SEL_PLL0
RBCK
SER_IN
VSSAA
VCM
VREFP
VCCAA
AOR+, AOR-
AOL-, AOL+
MIC1
MIC2
VREF
VREFM
RSET
COMP
VSSAV
CDAC
VCCAV
YDAC
VDAC
ACAP
XOUT
XIN
PCLK
2XPCLK
HSYN_B
VSYN_B
YUV[7:0]
24
2:4,27:30,76
33
37
41,51
42
43
44
45:46
47:48
49
50
52
53
54
55
56:57,62:63
58
59,60
61
64
65
71
74
79
80
82
84
86:89,92,94,96,98
O Reset output (active-low).
No connect.
O Dual-purpose. RSD is the receive audio data input.
I SEL_PLL0 and SEL_PLL1 select the PLL clock frequency for the DCLK output. Refer to the
table for pin 23.
O Dual-purpose. RBCK is the receive audio bit clock.
I SER_IN is the serial input DSC mode:
0 = Parallel DSC mode.
1 = Serial DSC mode.
I Audio analog ground.
I ADC common mode reference (CMR) buffer output. CMR is approximately 2.25V. Bypass to
analog ground with 47-µF electrolytic in parallel with 0.1 µF.
I DAC and ADC maximum reference. Bypass to video CMR (VCMR) with 10 µF in parallel with
0.1 µF.
I Analog VCC, 5V.
O Right channel output.
O Left channel output.
I Microphone input 1.
I Microphone input 2.
I Internal resistor divider generates CMR voltage. Bypass to analog ground with 0.1 µF.
I DAC and ADC minimum reference. Bypass to VCMR with 10 µF in parallel with 0.1 µF.
I Full-scale DAC current adjustment.
I Compensation pin.
I Video analog ground
O Modulated chrominance output.
I Video VCC, 5V
O Y luminance data bus for screen video port.
O Composite video output.
I Audio CAP
O Crystal output.
I 27-MHz crystal input.
I/O 13.5-MHz pixel clock.
I/O 27-MHz (2 times pixel clock).
O Horizontal sync (active-low).
O Vertical sync (active-low).
I YUV data bus for screen video port.
ESS Technology, Inc.
SAM0416-052201
3