ES2898 Datasheet, PDF (3/6 Pages) List of Unclassifed Manufacturers – V.90 PCI DSP Modem Solution

ES2898/ES2828 PRODUCT BRIEF
PIN DESCRIPTIONS
PIN DESCRIPTIONS
Table 1 lists the ES2898 pin descriptions. Table 2 lists the
ES2828 pin descriptions.
Table 1 ES2898 Pin Descriptions
Names
Pin Numbers I/O
Definitions
AD[16:31]
1:13, 98, 99, 100
I
When the ES2898 interfaces a PCI bus, these pins function as AD[16:31]. The PCI bus
implements a 32-bit multiplexed address and data bus.
GND
14, 20, 22, 41, 47, — Ground.
71, 90
C/BE[3:0]#
15, 21, 31, 32
Bus command/byte enable. These pins are multiplexed. During the address phase of a bus
I transaction, these pins define the bus command. During the data phase, these pins are used as
byte enables.
VDD
16, 18, 46, 48, 77, I Digital supply voltage, 3.3V.
83, 85, 93
VDD
17
I
When the ES2898 interfaces a PCI bus, use an internal chip select and tie the CS pin to this
VDD pin through a pullup 10k Ω resistor.
PERR#
19
O Parity error output.
AD[0:15]
23:30, 33:40
I/O
When the ES2898 interfaces a PCI bus, these pins function as AD[15:0]. The PCI bus
implements a 32-bit multiplexed address and data bus.
XTALI
42
I ES2898 clock input. This pin can be driven by either a crystal or an oscillator. When using a
crystal, XTALO is used as the other crystal pin. When using an oscillator, the output of the
oscillator is connected to XTALI. An internal clock doubler doubles the frequency at XTALI.
XTALO
43
O Works in conjunction with XTALI when a crystal is used. When an oscillator is used, XTALO is
left unconnected.
CLKOUT
44
O Fixed-frequency clock output. The frequency of this pin is the same as the crystal input of the
DSP clock. The clock is stopped during D2 and D3 states when the ST_CLKOUT bit is set.
BSEL1 / BSEL0
45, 61
I Used to determine the operating mode of the ES2898. These pins are sampled at the falling
edge of reset and are encoded as follows:.
Configuration
Reserved
Reserved
PCI interface
Generic 16-bit host interface
BSEL1 (pin 45)
0
0
1
1
BSEL0 (pin 61)
0
1
0
1
FL0
49
O Used as flag 0 output during normal operation.
FL1
50
O Used as flag 1 output during normal operation while the bypass circuitry is included. Will be
activated during power-down mode.
FL2
51
O Functions as flag 2 output during normal operation, and can also be used to provide a pass-
through reset to the ES2828. To bring the devices out of reset, write a logic zero. FL2 carries
the reset signal for the ES2828.
PF[7:0]
52, 53, 54, 55, 56, I/O General-purpose programmable bidirectional flag pins. These pins can be used for interfacing
57, 58, 59
with a telephone or other device, performing such functions as phone-off-hook, phone-on-hook,
ring, caller ID, etc. PF[0] is specially designed to support the ring function.
VDD(5V)
60
I Digital supply voltage. If the ES2898 interfaces with a 5V input, tie this pin to 5V. Otherwise, tie
this pin to 3.3V.
SEDO
62
I Serial EEPROM data input.
SECS
63
O Serial EEPROM chip select.
SEDI
64
O Serial EEPROM serial data output.
SECLK
65
O Serial EEPROM clock.
SCLK1
66
I/O One of two serial clock inputs. This clock can be generated either by the ES2898 or by the
ES2828.
ESS Technology, Inc.
SAM0402-050301
3