CMM1321 Datasheet, PDF (3/5 Pages) List of Unclassifed Manufacturers – 1.85 to 1.91 GHz 5V, 28.5 dBm, PCS Power Amplifier

Preliminary Product Information - November 1996
Typical Performance
CMM1321
(3 of 5)
Application Information
The CMM1321 is a two stage amplifier that requires a
positive and negative supply voltage for proper operation. It is
essential when turning on the device that the negative supply be
applied before the positive supply. When turning the device off,
the positive supply should be removed before the negative sup-
ply is removed.
The CMM1321 can be operated over a range of supply
voltages and bias points. It is important that the maximum
power dissipation of the package be observed at all times and
that the maximum voltage across the device, as specified, is not
exceeded.
Design Considerations
Biasing A negative voltage is needed to bias the 2 stage GaAs
FET power amplifier. The output stage is controlled via Vg2
and the input stage via Vg1.
The positive supply voltage is applied to pins 5, 6 and
7. The negative voltage supply should be adjusted to achieve the
typical quiescent current specified prior to characterization. The
RF input (pin 1) is internally DC blocked.
Matching Circuits Input and output matching circuits are
required. The CMM1321 evaluation board schematic and layout
are on page 4. The test board is designed to be used at multiple
frequencies. The matching elements for proper operation at
1.85–1.91 GHz are described on page 4.
A single shunt capacitor is used to match the output.
Note: Circuit board 8217 is a multiple-use test board.
The portions of the board that are used with the CMM1321 are
shown as solid traces on the board layout drawing on page 4.
The interface/connection points to the evaluation board are
shown. These connection points may not be labeled identically
on Celeritek’s PB-CMM1321 evaluation board. Contact the fac-
tory for support in translating the external match to a specific
application.
Supply Ramping To obtain the necessary power ramp, supply
side switching should be used. Drain voltages should be tied
together and ramped to produce the required power vs. time
response.
Modulation When biased as specified, the CMM1321 will
achieve the required adjacent channel response for the digital
PCS system specified. Celeritek tests each product under digital
modulation to ensure correlation to customer applications.
Thermal
1. The copper pad on the backside of the CMM1321 must be
soldered to the ground plane.
2. All 8 leads of the package must be soldered to the appropriate
electrical connection.
3. A large ground plane area with plated thru-holes as shown on
the PCB layout should be used as a backside connection.
Contact the factory for a copy of a manufacturing application
note containing more detailed information.
3236 Scott Boulevard
Santa Clara, California 95054
Phone: [phone]
Fax: [phone]