ANXPLORER Datasheet, PDF (3/4 Pages) List of Unclassifed Manufacturers – EDA TOOL FOR SCHEMATIC LEVEL OPTIMIZATION OF ANALOG & RF CIRCUITS

AnXplorer: EDA Tool for Schematic Level Optimization of Analog & RF Circuits
methodology for the synthesis of custom analog circuits”, Proc.
ICCAD 2001, pp 350-357. Shown in figure 3.
Technology: IBM 0.5um BSIM3v3 models, obtained from
http://www.mosis.org/test
METRIC
SPECIFICATION
RESULT
Gain
≥ 68 dB
72.6 dB
Unity gain BW
≥ 255 MHz
697 MHz
Phase margin
≥ 52 degrees
56 degrees
CMRR
≥ 55 dB
56.2 dB
PSRR (Vdd)
≥ 80 dB
86.5 dB
Slew rate
≥ 250 V/us
403 V/us
Propagation delay
≤ 2 ns
1.13 ns
Area
≤ 24000 sq. micron
6000 sq. micron
Figure 3: Two stage OpAmp schematic
Table 1: Specification and optimization for two stage OpAmp
Ultra wide-band OpAmp
Source: Advanced VLSI Design Lab, Indian Institute of Technol-
ogy, Kharagpur, shown in figure 4.
Technology: TSMC 0.18um BSIM3v3 models, obtained from
http://www.mosis.org/test
METRIC
SPECIFICATION
RESULT
Gain
≥ 60 dB
67.5 dB
Unity gain BW
≥ 2 GHz
2.18 GHz
Phase margin
≥ 50 degrees
55 degrees
ICMR
-
0.4 - 1.5 V
CMRR
-
86 dB
PSRR (Vdd)
-
83 dB
Settling time
-
3 ns
Static power
≤ 50 mW
46 mW
Table 2: Specification and optimization for ultra wide band
OpAmp
Missing entries in the specification column denote metrics which
were not part of the optimization objectives, but measured post
optimization.
High gain OpAmp
Source: Advanced VLSI Design Lab, Indian Institute of Technol-
ogy, Kharagpur, shown in figure 5.
Technology: TSMC 0.18um BSIM3v3 models, obtained from
http://www.mosis.org/test
Figure 4: Ultra wide-band OpAmp schematic
M7
node7
Vdd
M8
M5
bias
node6
M6
Rz ^Cc
node5
M3
node4
node3
M4
node2
VinN
M1
-+
+-
node0
node1 VinP
M2
M0
nbiias
gnd
M10
Vout
M9
Figure 5: High gain OpAmp schematic, with gain-booster stage
shown as a block.