22LV10AZ-25 Datasheet, PDF (3/10 Pages) List of Unclassifed Manufacturers – CMOS Programmable Electrically Erasable Logic Device

PEEL^TM 22LV10AZ
Function Description
The PEEL22LV10AZ implements logic functions as sum-of-products expressions in a programmable-AND/fixed-OR
logic array. User-defined functions are created by programming the connections of input signals into the array.
User-configurable output structures in the form of I/O macrocells further increase logic flexibility.
ICT has added optional enhanced capabilities to the PEEL22CV10A family of products with additional features and
added fuses to support them. Please view the comparison chart found below for the best algorithm
Algorithms
PEEL V10A Algorithm
PEEL V10A+ Algorithm
PEEL V10A++ Algorithm
Number of Fuses
5828
5873
5958
Supported Features
Standard 22V10 JEDEC
Compatible
Superset of standard
22V10
Superset of standard
22V10 (recommended for
new designs)
4 macrocell options
12 macrocell options
12 macrocell options
3 byte signature word
8 byte signature word
Security bit
Security bit
Clock source selection
Clock polarity selection
Table 1 - Programming Algorithm Comparison
Architecture Overview
The PEEL22LV10AZ architecture is illustrated in the
block diagram of Figure 2. Twelve dedicated inputs and
10 I/Os provide up to 22 inputs and 10 outputs for
creation of logic functions. At the core of the device is a
programmable electrically erasable AND array that
drives a fixed OR array. With this structure, the
PEEL22LV10AZ can implement up to 10 sum-of-
products logic expressions.
Associated with each of the ten OR functions is an I/O
macrocell that can be independently programmed to
one of 12 different configurations, including the four
standard 22V10 modes. The programmable macrocells
allow each I/O to be used to create sequential or
combinatorial logic functions of active-high or active-low
polarity, while providing three different feedback paths
into the AND array.
AND/OR Logic Array
The programmable AND array of the PEEL22LV10AZ
(shown in Figure 3) is formed by input lines intersecting
product terms. The input lines and product terms are
used as follows:
• 44 Input Lines:
- 24 input lines carry the true and complement
of the signals applied to the 12 input pins
- 20 additional lines carry the true and
complement values of feedback or input
signals from the 10 I/Os
• 133 Product Terms:
- 120 product terms (arranged in 2 groups of 8,
10, 12, 14, and 16) are used to form sum of
product functions
- 10 outputs enable terms (one for each I/O)
- 1 global synchronous preset term
- 1 global asynchronous clear term
- 1 programmable clock term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not
there is a logical connection at that intersection. Each
product term is essentially a 44-input AND gate. A
product term that is connected to both the true and
complement of an input signal will always be FALSE
and thus will not affect the OR function that it drives.
When all the connections on a product term are
opened, a "don't care" state exists and that term will
always be TRUE.
When programming the PEEL22LV10AZ, the device
programmer first performs a bulk erase to remove the
previous pattern. The erase cycle opens every logical
connection in the array. The device is configured to
perform the user-defined function by programming
selected connections in the AND array. (Note that PEEL
device programmers automatically program all of the
connections on unused product terms so that they will
have no effect on the output function).
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