SA25F020 Datasheet, PDF (29/37 Pages) List of Unclassifed Manufacturers – 2Mb Serial Flash with 25MHz SPI Bus Interface

Bulk Erase (BE)
The BE instruction sets all bits in the
memory array to 1. Before it can be
executed, two separate instructions must
be carried out. The device must first be
write enabled via the WREN instruction,
and then a BE sequence, which consists of
four bytes plus data, may be executed. The
address of the memory locations to be
written must be outside the protected
address field location selected by the Block
Write Protection level. During an internal
BE cycle, all commands are ignored except
the RDSR instruction.
A BE instruction requires the following
sequence:
1. After the CSb line is pulled low to
select the device, the BE opcode is
transmitted via the SI line.
2. Erasing begins after the CSb pin is
brought high. The CSb pin's
low-to-high transition must occur
during the SCK low time,
immediately after the clock in the
last opcode bit.
CS
SA25F020 Advanced Information
SAIFUN
29
As soon as CSb is driven high, the
self-timed BE cycle (whose duration is
defined as T_BE) is initiated. While the BE
cycle is in progress, the status register may
be read to check the value of the /RDY bit.
The /RDY bit is 1 during the self-timed BE
cycle, and 0 when it is completed. The
WEN bit is reset at some unspecified time
before the cycle is completed. The
instruction sequence is shown in Figure 19.
The SA25F020 is automatically returned to
the Write Disable state at the completion of
a BE cycle.
NOTES:
1. If the device is not write enabled,
the device ignores the BE
instruction and returns to the
standby state when CSb is brought
high. A new CSb falling edge is
required to re-initiate the serial
communication.
2. A BE instruction can be applied
only if both Block Protect (BP1,
BP0) bits (as described in Table 8,
page 18, and Table 9, page 21)
are 0.
SCK
SI
01 2 34 5 6 7
Instruction
Figure 19. Bulk Erase (BE) Instruction Sequence