RTL8100C Datasheet, PDF (28/73 Pages) List of Unclassifed Manufacturers – SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT

Bit
15~13
12, 11
10~8
7
6
R/W
R/W
R/W
R/W
R/W
-
RTL8100C & RTL8100CL
Datasheet
Symbol
RXFTH2, 1, 0
RBLEN1, 0
MXDMA2, 1, 0
WRAP
-
Description
Rx FIFO Threshold.
Specifies the Rx FIFO Threshold level. When the number of received
data bytes from a packet that is being received into the RTL8100C(L)’s
Rx FIFO has reached this level (or the FIFO contains a complete
packet), the receive PCI bus master function will begin to transfer the
data from the FIFO to the host memory. This field sets the threshold
level according to the following table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = No Rx threshold. The RTL8100C(L) begins the transfer of data
after receiving a whole packet in the FIFO.
Rx Buffer Length.
This field indicates the size of the Rx ring buffer:
00 = 8k + 16 bytes
01 = 16k + 16 bytes
10 = 32K + 16 bytes
11 = 64K + 16 bytes
Max DMA Burst Size per Rx DMA Burst.
This field sets the maximum size of the receive DMA data bursts:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = Unlimited
Wraps packet data into the beginning of the Rx buffer.
0: The RTL8100C(L) will transfer the rest of the packet data into the
beginning of the Rx buffer if this packet has not been completely moved into
the Rx buffer and the transfer has arrived at the end of the Rx buffer.
1: The RTL8100C(L) will keep moving the rest of the packet data into
the memory immediately after the end of the Rx buffer, if this packet has
not been completely moved into the Rx buffer and the transfer has
arrived at the end of the Rx buffer. The software driver must reserve at
least 1.5 Kbytes buffer to accept the remainder of the packet. We assume
that the remainder of the packet is X bytes. The next packet will be
moved into the memory from the X byte offset at the top of the Rx
buffer.
This bit is invalid when the Rx buffer is set to 64 Kbytes.
Reserved.
Single-Chip Fast Ethernet Controller
20
Track ID: JATR-1076-21 Rev. 1.06