FM8P51 Datasheet, PDF (26/60 Pages) List of Unclassifed Manufacturers – EPROM/ROM-Based 8-Bit Microcontroller

FEELING
TECHNOLOGY
FM8P51
2.6 PWM (Pulse Width Modulation) Module
Two high speed pulse width modulation (PWM) outputs are provided. The PWM0 output uses Timer2 as its time
base, the PWM1 may be configured to use Timer2 or Timer3 as the time base. The PWM outputs are on the
IOA0/PWM0, and IOC0/PWM1 pins.
Each PWM output has a maximum resolution of 10-bits. The duty cycle of the output can vary from 0% to 100%.
The user needs to set the PW0ON bit (PWMCON<0>) to enable the PWM output. When PW0ON bit is set, the
IOA0/PWM0 pin is configured as PWM0 output and forced as an output, irrespective of the data direct bit
(IOSTA<0>). When the PW0ON is clear, the pin behaves as a port pin.
Similarly, the PW1ON bit (PWMCON<1>) controls the configuration of the IOC0/PWM1 pin.
2.6.1 PWM Periods
The period of PWM0 output is determined by Timer2 and its period register (PR2). The period of the PWM1 output
can be software configured to use either Timer2 or Timer3 as the time base. For PWM1, when PW1T3 bit
(PWMCON<2>) is clear, the time base is determined by TMR2 and PR2, and when PW1T3 bit is set, the time base
is determined by TMR3 and PR3.
Running two different PWM outputs on two different timers allows different periods. Running all PWMs from Timer2
allows the best use of resources by freeing Timer3 to operate as an 8-bit timer. Timer2 and Timer3 cannot be used
as a 16-bit timer if any PWM is being used.
The PWM periods can be calculated as follows:
Period of PWM0 = [(PR2) + 1] x 4Tosc
Period of PWM1 = [(PR2) + 1] x 4Tosc or
[(PR3) + 1] x 4Tosc
The duty cycle of PWMx is determined by the 10-bit value DCx<9:0>. The upper 8-bits are from register PWxDCH
and lower2-bits are from PWxDCL<7:6> (PWxDCH:PWxDCL<7:6>).
The PWMx duty cycle is as follows:
PWMx Duty Cycle = (DCx) x Tosc
Where DCx represents the 10-bit value from PWxDCH:PWxDCL.
If DCx = 0, then the duty cycle is zero. If PRx = PWxDCH, then the PWM output will be low for one to four Tosc
(depending on the state of the PWxDCL<7:6> bits). For a duty cycle to be 100%, the PWxDCH value must be
greater then the PRx value.
The duty cycle registers for both PWM outputs are double buffered. When the user writes to these registers, they
are stored in master latches. When TMR2 (or TMR3) overflows and a new PWM period beings, the master latch
values are transferred to the slave latches.
2.6.2 PWM Interrupts
The PWM modules make use of the TMR2 and/or TMR3 interrupts. A timer interrupt is generated when TMR2 or
TMR3 equals its period register and on the following increment is cleared to zero. This interrupt also marks the
beginning of a PWM cycle. The user can write new duty cycle values before the timer rollover. The TMR2 interrupt is
latched into the T2IF bit and the TMR3 interrupt is latched into the T3IF bit. These flags must be cleared in software.
Rev1.2 Mar 15, 2005
P.26/FM8P51