A54SX16 Datasheet, PDF (26/57 Pages) List of Unclassifed Manufacturers – 54SX Family FPGAs

54SX Family FPGAs
A54SX08 Timing Characteristics (continued)
(Worst-Case Commercial Conditions)
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed
Parameter Description
Min. Max. Min. Max. Min. Max. Min. Max. Units
Dedicated (Hard-Wired) Array Clock Network
t_HCKH
Input LOW to HIGH
(Pad to R-Cell Input)
t_HCKL
Input HIGH to LOW
(Pad to R-Cell Input)
t_HPWH
t_HPWL
t_HCKSW
t_HP
f_HMAX
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
Minimum Period
Maximum Frequency
Routed Array Clock Networks
1.0
1.1
1.3
1.5 ns
1.0
1.2
1.4
1.6 ns
1.4
1.6
1.8
2.1
ns
1.4
1.6
1.8
2.1
ns
0.1
0.2
0.2
0.2 ns
2.7
3.1
3.6
4.2
ns
350
320
280
240 MHz
t_RCKH
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input)
t_RCKL
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input)
t_RCKH
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input)
t_RCKL
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input)
t_RCKH
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input)
t_RCKL
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input)
t_RPWH
Min. Pulse Width HIGH
t_RPWL
Min. Pulse Width LOW
t_RCKSW
Maximum Skew (Light Load)
t_RCKSW
Maximum Skew (50% Load)
t_RCKSW
Maximum Skew (100% Load)
TTL Output Module Timing¹
1.3
1.5
1.7
2.0 ns
1.4
1.6
1.8
2.1 ns
1.4
1.7
1.9
2.2 ns
1.5
1.7
2.0
2.3 ns
1.5
1.7
1.9
2.2 ns
1.5
1.8
2.0
2.3 ns
2.1
2.4
2.7
3.2
ns
2.1
2.4
2.7
3.2
ns
0.1
0.2
0.2
0.2 ns
0.3
0.3
0.4
0.4 ns
0.3
0.3
0.4
0.4 ns
t_DLH
Data-to-Pad LOW to HIGH
1.6
1.9
2.1
t_DHL
Data-to-Pad HIGH to LOW
1.6
1.9
2.1
t_ENZL
Enable-to-Pad, Z to L
2.1
2.4
2.8
t_ENZH
Enable-to-Pad, Z to H
2.3
2.7
3.1
t_ENLZ
Enable-to-Pad, L to Z
1.4
1.7
1.9
t_ENHZ
Enable-to-Pad, H to Z
1.3
1.5
1.7
Note:
1. Delays based on 35 pF loading, except t_ENZL and t_ENZH . For t_ENZL and t_ENZH the loading is 5 pF.
2.5
ns
2.5 ns
3.2
ns
3.6
ns
2.2 ns
2.0 ns
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