LM3S1911 Datasheet, PDF (256/426 Pages) List of Unclassifed Manufacturers – Microcontroller

Universal Asynchronous Receivers/Transmitters (UARTs)
Figure 12-3. IrDA Data Modulation
UnTx
Start
bit
0
1
0
1
UnTx with IrDA
UnRx with IrDA
Bit period
Data bits
0
0
1
1
Stop
bit
0
1
3
16
Bit period
UnRx
0
1
Start
0
1
0
0
Data bits
1
1
0
1
Stop
12.2.5
12.2.6
In both normal and low-power IrDA modes:
■ During transmission, the UART data bit is used as the base for encoding
■ During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased, or even saturated from the optical power coupled from the adjacent transmitter
LED. This delay is known as latency, or receiver setup time.
FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed
via the UART Data (UARTDR) register (see page 260). Read operations of the UARTDR register
return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data
in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 269).
FIFO status can be monitored via the UART Flag (UARTFR) register (see page 264) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The
UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the
UARTRSR register shows overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 273). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For
example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt
after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the
½ mark.
Interrupts
The UART can generate interrupts when the following conditions are observed:
■ Overrun Error
■ Break Error
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October 09, 2007
Preliminary