PS2500 Datasheet, PDF (24/28 Pages) List of Unclassifed Manufacturers – Low-Power Direct Digital Modulation Frequency Synthesizer

PS2500 2.2 GHz Fractional-N Frequency Synthesizer
• Main Synthesizer Power Down = 1-bit value for powering down the main synthesizer. When this bit is 0,
the main synthesizer is powered up. When this bit is 1, the main synthesizer is in power down mode.
• Main Synthesizer Mode = 1-bit value for powering down the main synthesizer’s ∆Σ modulator and
fractional unit to operate as a integer-N synthesizer. When this bit is 0, the main synthesizer is in
fractional-N mode. When this bit is 1, the main synthesizer is in integer-N mode.
• Main Synthesizer ∆Σ Fractionality = 1-bit value to configure the size of the main ∆Σ modulator. This
has a direct effect on power consumption and on the level of fractionality and step size. When this bit is
0, the main ∆Σ modulator is 18-bit with fractionality of 2¹⁸ and step size of F_{ref_main}/262144. When this
bit is 1, the main ∆Σ modulator is 10-bit with fractionality of 2¹⁰ and step size of F_{ref_main}/1024.
• Auxiliary Synthesizer Power Down = 1-bit value for powering down the auxiliary synthesizer. When this
bit is 0, the auxiliary synthesizer is powered up. When this bit is 1, the auxiliary synthesizer is in
power-down mode.
• Auxiliary Synthesizer Mode = 1-bit value for powering down the auxiliary synthesizer’s ∆Σ modulator
and fractional unit to operate as a integer-N synthesizer. When this bit is 0, the auxiliary synthesizer is in
fractional-N mode. When this bit is 1, the auxiliary synthesizer is in integer-N mode.
Note: There are no special power up sequences required for the PS2500.
• Multiplexer Output Selection = 3-bit value for selecting which internal signal is output to the Mux_out
pin. Internal signals available on this pin are:
— Reference Oscillator: F_ref
— Main or auxiliary divided reference (post reference frequency main or auxiliary dividers): F_{ref_main}
or F_{ref_aux}
— Main or auxiliary phase detector frequency (post main and auxiliary frequency dividers): F_{pd_main} or
F_{pd_aux}
— Serial data out, for loop-back and test purposes
Refer to the following table for more information.
Table 10: Multiplexer Output
Multiplexer
Output Select
bit 2
Multiplexer
Output Select
bit 1
Multiplexer
Output Select
bit 0
Multiplexer Output
(Mux_out)
0
0
0
Reference Oscillator
0
0
1
Auxiliary Reference Frequency (F_{ref_aux})
0
1
0
Main Reference Frequency (F_{ref_main})
0
1
1
Auxiliary Phase Detector Frequency (F_{pd_aux})
1
0
0
Main Phase Detector Frequency (F_{pd_main})
1
0
1
Serial Data Out
1
1
0
Serial Interface Register Test Output
Philsar Semiconductor Inc.
146 Colonnade Road S.
Nepean, Ontario, Canada
K2E 7Y1
- 24 -
Tel: [phone]
Fax: [phone]
www.philsar.com
PMP-001-DS2 V1.2