EPXA10 Datasheet, PDF (24/25 Pages) List of Unclassifed Manufacturers – EPXA10

EPXA10F1020 Pin Tables
ver. 1.4
Notes:
(1) This pin can be used as a user I/O pin after configuration.
(2) This pin is the power or ground for the ClockLock and ClockBoost circuitry. To ensure noise resistance,
the power and ground supply to the ClockLock and ClockBoost circuitry should be isolated from the
power and ground to the rest of the device. VCC_CKLK has the same voltage specifications as the
VCCINT and should be connected to a 1.8 -V power supply. If the ClockLock or ClockBoost circuitry is
not used, this power or ground pin should be connected to VCCINT or GNDINT, respectively.
(3) This pin can be used as a user I/O pin if it is not used for its device-wide or configuration function.
(4) This pin is the complementary signal for the LVDS pair on dedicated inputs and outputs that can be
configured for the LVDS standard. If not used for the LVDS pair, these pins are regular I/O pins. Pins
with the "n" suffix carry the negative signal for the LVDS channel. Pins with a "p" suffix carry the positive
signal for the LVDS channel.
(5) This pin is a dedicated pin; it is not available as a user I/O pin.
(6) This pin is tri-stated in user mode.
(7) This pin is the power or ground for the external output of a PLL. These pins should be set to the VCCIO
level/standard desired for the external clock ouput. To ensure noise resistance, the power and ground
supply to the PLL external output should be isolated from the power and ground to the rest of the VCCIO
and GNDIO pins. If the PLL or external output is not used, this power or ground pin should be connected
to VCCIO or GNDIO, respectively.
(8) The CLKLK_OUT pin is powered by the VCC_CKOUT and GND_CKOUT pins.
(9) This pin shows the status of the ClockLock and ClockBoost circuitry. When the ClockLock and
ClockBoost circuitry is locked to the incoming clock and generates an internal clock, LOCK is driven
high. LOCK will go low if a periodic clock stops clocking the input to the PLL. The LOCK function is optional; if the LOCK
output is not used, this pin is a user I/O pin.
(10) This pin is the active high enable pin for all of the PLL circuits in the device. When de-asserted, all PLLs
are reset to their default, unlocked state and will stop clocking. Once re-asserted, the PLLs will lock
again and start clocking. If this pin function is not needed, the pin should be connected to VCCINT.
(11) The user I/O pin count includes dedicated FAST I/Os and dedicated clock inputs. It does not include the
dedicated clock feedback and output pins.
(12) This pin is reserved for future functionality and should be connected to GND for this device.
Altera Corporation
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