73M2910L Datasheet, PDF (23/35 Pages) List of Unclassifed Manufacturers – Microcontroller

RESET (option to set)
COMPUTE
DATA
AND2
C8 C1
73M2910L
Microcontroller
C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
C15
CRC 16 X¹⁶ + X¹⁵ + X² + 1
MUX OUT
FIGURE 4: CRC 16
CRC 16
The CRC check field is generated by the transmitter. The computation starts with the first transmitted bit after
the opening flag and stops at the last data bit prior to the frame check sequence bytes, and excludes inserted
0s. The CRC generating logic is initialized to all 0s. The bits are shifted in and operated on by the generating
polynomial, X¹⁶ + X¹² + X⁵ + 1. During CRC transmission, the bytes in the CRC generating logic are
transmitted, high order bit first.
The receiver also initializes its CRC computation logic to all ones after the beginning flag. Its polynomial
generator (also X¹⁶ + X¹² + X⁵ + 1) should see the same value as the transmitter’s polynomial generator as
the last data bit is received. Note the receiver’s polynomial generator does not process inserted 0s. After the
bytes are received in the frame check sequence, a remainder of 1111 0000 1011 1000 should be detected in
the receiver’s polynomial generator. If this is not the case, it is assumed that the preceding frame was in error
and an invalid CRC is declared.
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