NX5850 Datasheet, PDF (22/152 Pages) List of Unclassifed Manufacturers – Digital Audio SoC

NX5850
Digital Audio SoC
Preliminary
5. System Clock Control
NX5850 has one PLL with external Crystal Oscillator input and system internal clock source is supplied by
PLL output through several divider to each function block. Each function block clock is divider output
frequency which is PLL output frequency divided by divider value. User sets PLL coefficient register value for
PLL out put frequency control and sets divider register value to determine divider output frequency.
12MHz
PLL Out = 192MHz
PLL
MUX
PLL Coefficient
0xFF11
0xFF12
8bit
divider
divider Out
External
Crystal
32.768KHz
Bypass
8bit
divider
16bit
divider
System Block
MCU Block
ADC Block
MP3 Block
I2S Interface Block
External
Crystal
MUX
RTC
divider Coefficient
0xFF13 ~ 0xFF18
NX5855 Only
8 bit divider Out = (PLL Out) x (divider coefficient) / 0x100
16 bit divider out = (PLL Out) x (divider coefficient) / 0x10000
Figure 6. The Diagram of the Clock Distribution
5.1. Clock Source Control Register
Table 17. Clock source control Register Map (P2 = 0xFF)
Function
Address
(Hex)
Type
Reset
Description
CLOCK_SOURCE_CONTROL
0x04
R/W 0x07 Clock Source Control
DEFAULT_COEFFICIENT_ENABLE
PLL_COEFFICIENT_LO
PLL_COEFFICIENT_HI
DIVIDER_COEFFICIENT_VALUE
0x10
0x11
0x12
0x13
~0x18
R/W
R/W
R/W
0x1f
0x00
0x00
Use Default PLL and divider coefficient
Controls PLL Output Frequency
R/W 0x00 Controls divider Output Frequency
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