GM5020 Datasheet, PDF (22/86 Pages) List of Unclassifed Manufacturers – Graphics Processing IC providing high-quality images for LCD monitors and other pixelated displays

Genesis Microchip
gm5020 / gm5020-H Data Sheet
4.1 Clocking Options
The gm5020 features four clock inputs:
1) Timing Clock (TCLK). This is a required clock used as a reference frequency source for
the gm5020. Additional clocks are synthesized internally using this reference. TCLK
may be connected to a crystal resonator or external oscillator and is further described
below.
2) DVI Differential Input Clock (RC+ and RC-). Provided by the external DVI interface.
3) Video Clock (VCLK) input pin. Provided by the external video decoder.
4) Host Interface Transfer Clock (HCLK for 6-Wire nibble; SCL for 2-wire serial). Provided
by the external micro controller (MCU).
4.1.1 TCLK Requirements
The TCLK may be generated using either a crystal resonator circuit (recommended) or an
external clock oscillator. The TCLK frequency should range between 14 and 50 MHz, though 24
MHz is preferred.
If TCLK is derived from a crystal resonator, an internal oscillator circuit generates a very low
jitter and low harmonic clock within the gm5020. The crystal should be connected between the
XTAL and TCLK pins and utilize appropriately sized loading capacitors. C_L1 and C_L2 are
terminated to AVDD_33 to increase the power supply rejection ratio. This is shown in the
diagram below.
AVDD_33
CL1
(5pF typ)
AVDD_33
CL2
(5pF typ)
J4
TCLK
H4
XTAL
gm5020
Vdd
100 K
180 uA
OSC_OUT
TCLK Distribution
Figure 4. TCLK connection (with Crystal Resonator)
The size of C_L1 and C_L2 are determined from the crystal manufacturer’s specification and the
parasitic capacitance of the gm5020 and PCB traces. To avoid start up problems with the internal
oscillator, the C_LOAD parameter specified by the crystal manufacturer should not be exceeded.
C_LOAD includes C_L1, C_L2 as well as the parasitic capacitances. Specifically, these include the
February 2002
13
C5020-DAT-01Q