ARM7TDMI Datasheet, PDF (217/268 Pages) List of Unclassifed Manufacturers – general purpose 32-bit microprocessors

ICEBreaker Module
9.3.1 Hardware breakpoints
To make a watchpoint unit cause hardware breakpoints (ie on instruction fetches):
1 Program its Address Value register with the address of the instruction to be
breakpointed.
2 For a breakpoint in ARM state, program bits [1:0] of the Address Mask register
to 1. For a breakpoint in THUMB state, program bit 0 of the Address Mask to
1. In both cases the remaining bits are set to 0.
3 Program the Data Value register only if you require a data-dependent
breakpoint: ie only if the actual instruction code fetched must be matched as
well as the address. If the data value is not required, program the Data Mask
register to 0xFFFFFFFF (all bits to1), otherwise program it to0x00000000.
4 Program the Control Value register with nOPC = 0.
5 Program the Control Mask register with nOPC =0, all other bits to 1.
6 If you need to make the distinction between user and non-user mode
instruction fetches, program the nTRANS Value and Mask bits as above.
7 If required, program the EXTERN, RANGE and CHAIN bits in the same way.
9.3.2 Software breakpoints
To make a watchpoint unit cause software breakpoints (ie on instruction fetches of a
particular bit pattern):
1 Program its Address Mask register to 0xFFFFFFFF (all bits set to 1) so that
the address is disregarded.
2 Program the Data Value register with the particular bit pattern that has been
chosen to represent a software breakpoint.
If a THUMB software breakpoint is being programmed, the 16-bit pattern must
be repeated in both halves of the Data Value register. For example, if the bit
pattern is 0xDFFF, then 0xDFFFDFFF must be programmed. When a 16-bit
instruction is fetched, ICEbreaker only compares the valid half of the data bus
against the contents of the Data Value register. In this way, a single
Watchpoint register can be used to catch software breakpoints on both the
upper and lower halves of the data bus.
3 Program the Data Mask register to 0x00000000.
4 Program the Control Value register with nOPC = 0.
5 Program the Control Mask register with nOPC = 0, all other bits to 1.
6 If you wish to make the distinction between user and non-user mode
instruction fetches, program the nTRANS bit in the Control Value and Control
Mask registers accordingly.
7 If required, program the EXTERN, RANGE and CHAIN bits in the same way.
Note The address value register need not be programmed.
ARM7TDMI Data Sheet
9-7
ARM DDI 0029E