LM3S811 Datasheet, PDF (210/410 Pages) List of Unclassifed Manufacturers – Microcontroller

Analog-to-Digital Converter (ADC)
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C
This register provides the mechanism for clearing interrupt conditions, and shows the status of
controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical
AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the
corresponding bit position. If software is polling the ADCRIS instead of generating interrupts, the
INR bits are still cleared via the ADCISC register, even if the IN bit is not set.
ADC Interrupt Status and Clear (ADCISC)
Offset 0x00C
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
IN3 IN2 IN1 IN0
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W1C
R/W1C
R/W1C
R/W1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
2
1
0
Name
reserved
IN3
IN2
IN1
IN0
Type
RO
R/W1C
R/W1C
R/W1C
R/W1C
Reset
0
0
0
0
0
Description
Reserved bits return an indeterminate value, and should never
be changed.
This bit is set by hardware when the MASK3 and INR3 bits are
both 1, providing a level-based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR3 bit.
This bit is set by hardware when the MASK2 and INR2 bits are
both 1, providing a level based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR2 bit.
This bit is set by hardware when the MASK1 and INR1 bits are
both 1, providing a level based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR1 bit.
This bit is set by hardware when the MASK0 and INR0 bits are
both 1, providing a level based interrupt to the controller. It is
cleared by writing a 1, and also clears the INR0 bit.
210
October 8, 2006
Preliminary