XE88LC02 Datasheet, PDF (21/184 Pages) List of Unclassifed Manufacturers – Sensing Machine Data Acquisition MCU with 16 + 10 bit ZoomingADC and LCD driver

Datasheet XE88LC02 Sensing
Machine Data Acquisition MCU
with Zooming ADC and LCD driver
3.3 CPU instruction short reference
Table 3-4 shows a short description of the different instructions available on the Coolrisc816. The
notation cc in the conditional jump instruction refers to the condition description as given in Table 3-6.
The notation reg, reg1, reg2, reg3 refers to one of the CPU internal registers of Table 3-1. The
notation eaddr and DM(eaddr) refer to one of the extended address modes as defined in Table 3-5.
The notation DM(xxx) refers to the data memory location with address xxx.
Instruction
Jump addr[15:0]
Jump ip
Jcc addr[15:0]
Jcc ip
Call addr[15:0]
Call ip
Calls addr[15:0]
Calls ip
Ret
Rets
Reti
Push
Pop
Move reg,#data[7:0]
Move reg1, reg2
Move reg, eaddr
Move eaddr, reg
Move addr[7:0],#data[7:0]
Cmvd reg1, reg2
Cmvd reg, eaddr
Cmvs reg1, reg2
Cmvs reg, eaddr
Shl reg1, reg2
Shl reg
Shl reg, eaddr
Shlc reg1, reg2
Shlc reg
Shlc reg, eaddr
Shr reg1, reg2
Shr reg
Shr reg, eaddr
Shrc reg1, reg2
Shrc reg
Shrc reg, eaddr
Shra reg1, reg2
Shra reg
Shra reg, eaddr
Cpl1 reg1, reg2
Cpl1 reg
Cpl1 reg, eaddr
Cpl2 reg1, reg2
Cpl2 reg
Cpl2 reg, eaddr
Cpl2c reg1, reg2
Cpl2c reg
Cpl2c reg, eaddr
Inc reg1, reg2
Inc reg
Inc reg, eaddr
Incc reg1, reg2
Incc reg
Incc reg, eaddr
Dec reg1, reg2
Modification Operation
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
PC := addr[15:0]
PC := ip
if cc is true then PC := addr[15:0]
if cc is true then PC := ip
ST_n+1 := ST_n (n>1); ST₁ := PC+1; PC := addr[15:0]
ST_n+1 := ST_n (n>1); ST₁ := PC+1; PC := ip
ip := PC+1; PC := addr[15:0]
ip := PC+1; PC := ip
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-,-, -
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-,-, -
-,-,-, -
PC := ST₁; ST_n := ST_n+1 (n>1)
PC := ip
PC := ST₁; ST_n := ST_n+1 (n>1); GIE :=1
PC := PC+1; ST_n+1 := ST_n (n>1); ST₁ := ip
PC := PC+1; ip := ST₁; ST_n := ST_n+1 (n>1)
a := data[7:0]; reg := data[7:0]
a := reg2; reg1 := reg2
a := DM(eaddr); reg := DM(eaddr)
DM(eaddr) := reg
DM(addr[7:0]) := data[7:0]
-,-, Z, a
-,-, Z, a
-,-, Z, a
-,-, Z, a
a := reg2; if C=0 then reg1 := a;
a := DM(eaddr); if C=0 then reg := a
a := reg2; if C=1 then reg1 := a;
a := DM(eaddr); if C=1 then reg := a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := reg2<<1; a[0] := 0; C := reg2[7]; reg1 := a
a := reg<<1; a[0] := 0; C := reg[7]; reg := a
a := DM(eaddr)<<1; a[0] :=0; C := DM(eaddr)[7]; reg := a
a := reg2<<1; a[0] := C; C := reg2[7]; reg1 := a
a := reg<<1; a[0] := C; C := reg[7]; reg := a
a := DM(eaddr)<<1; a[0] := C; C := DM(eaddr)[7]; reg := a
a := reg2>>1; a[7] := 0; C := reg2[0]; reg1 :=a
a := reg>>1; a[7] := 0; C := reg[0]; reg := a
a := DM(eaddr)>>1; a[7] := 0; C := DM(eaddr)[0]; reg := a
a := reg2>>1; a[7] := C; C := reg2[0]; reg1 := a
a := reg>>1; a[7] := C; C := reg[0]; reg := a
a := DM(eaddr)>>1; a[7] := C; C := DM(eaddr)[0]; reg := a
a := reg2>>1; a[7] := reg2[7]; C := reg2[0]; reg1 := a
a := reg>>1; a[7] := reg[7]; C := reg[0]; reg := a
a := DM(eaddr)>>1; a[7] := DM(eaddr)[7]; C := DM(eaddr)[0]; reg := a
-,-, Z, a
-,-, Z, a
-,-, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := NOT(reg2); reg1 := a
a := NOT(reg); reg := a
a := NOT(DM(eaddr)); reg := a
a := NOT(reg2)+1; if a=0 then C:=1 else C := 0; reg1 := a
a := NOT(reg)+1; if a=0 then C:=1 else C := 0; reg := a
a := NOT(DM(eaddr))+1; if a=0 then C:=1 else C := 0; reg := a
a := NOT(reg2)+C; if a=0 and C=1 then C:=1 else C := 0; reg1 := a
a := NOT(reg)+C; if a=0 and C=1 then C:=1 else C := 0; reg := a
a := NOT(DM(eaddr))+C; if a=0 and C=1 then C:=1 else C := 0; reg := a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
C, V, Z, a
a := reg2+1; if a=0 then C := 1 else C := 0; reg1 := a
a := reg+1; if a=0 then C := 1 else C := 0; reg := a
a := DM(eaadr)+1; if a=0 then C := 1 else C := 0; reg := a
a := reg2+C; if a=0 and C=1 then C := 1 else C := 0; reg1 := a
a := reg+C; if a=0 and C=1 then C := 1 else C := 0; reg := a
a := DM(eaadr)+C; if a=0 and C=1 then C := 1 else C := 0; reg := a
a := reg2-1; if a=hFF then C := 0 else C := 1; reg1 := a
3-4
D0207-134