KAD5512P-50 Datasheet, PDF (21/28 Pages) List of Unclassifed Manufacturers – 12-Bit, 500MSPS A/D Converter

KAD5512P-50
Setting this bit high resets all SPI registers to
default values.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to
avoid ambiguity in bit ordering.
Address 0x02: burst_end
If a series of sequential registers are to be set, burst
mode can improve throughput by eliminating redun-
dant addressing. In 3-wire SPI mode the burst is
ended by pulling the CSB pin high. If the device is
operated in 2-wire mode the CSB pin is not available.
In that case, setting the burst_end address deter-
mines the end of the transfer. During a write opera-
tion, the user must be cautious to transmit the correct
number of bytes based on the starting and ending
addresses.
Bits 7:0 Burst End Address
This register value determines the ending ad-
dress of the burst data.
DUT Information
Address 0x08: chip_id
Address 0x09: chip_version
The generic die identifier and a revision number, re-
spectively, can be read from these two registers.
Indexed DUT Configuration/Control
Address 0x10: device_index_A
Bits 1:0 ADC01, ADC00
Determines which ADC is addressed. Valid
states for this register are 0x01 or 0x10. The two
ADC cores cannot be adjusted concurrently.
A common SPI map, which can accommodate sin-
gle-channel or multi-channel devices, is used for all
Kenet ADC products. Certain configuration com-
mands (identified as Indexed in the SPI map) can be
executed on a per-converter basis. This register de-
termines which converter is being addressed for an
Indexed command. It is important to note that only a
single converter can be addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed.
Address 0x20: offset_coarse
Address 0x21: offset_fine
The input offset of the ADC core can be adjusted in
fine and coarse steps. Both adjustments are made
via an 8-bit word as detailed in Table 7. The data for-
mat is twos complement.
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incre-
mented or decremented value back to the same
register.
Parameter
0x20[7:0]
Coarse Offset
0x21[7:0]
Fine Offset
Steps
–Full Scale (0x80)
Mid–Scale (0x00)
+Full Scale (0x7F)
Nominal Step Size
256
-24.0mV
0.0mV
+23.8mV
187.5µV
256
-1.7mV
0.0mV
+1.7mV
13.3µV
Table 7. Offset Adjustments
Address 0x22: gain_coarse
Address 0x23: gain_medium
Address 0x24: gain_fine
Gain of the ADC core can be adjusted in coarse,
medium and fine steps. Coarse gain is a 4-bit adjust-
ment while medium and fine are 8-bit. The data for-
mat is twos complement for all three registers.
The default value of each register will be the result of
the self-calibration after initial power-up. If a register is
to be incremented or decremented, the user should
first read the register value then write the incre-
mented or decremented value back to the same
register.
Parameter
Steps
–Full Scale (0x08)
Mid–Scale (0x00)
+Full Scale (0x07)
Nominal Step Size
0x22[3:0]
Coarse Gain
16
-11.2%
0.0%
+9.8%
1.4%
Table 8. Coarse Gain Adjustment
Rev 0.5.1 Preliminary
Page 21