DS21Q55 Datasheet, PDF (203/237 Pages) List of Unclassifed Manufacturers – Quad T1/E1/J1 Transceiver

Table 30-B. ID Code Structure
MSB
Version
Contact Factory
Device ID
JEDEC
4 bits
16 bits
00010100001
DS21Q55 Quad T1/E1/J1 Transceiver
LSB
1
1
Table 30-C. Device ID Codes
PART
16-BIT ID
DS2155
DS2156
DS21354
DS21554
DS21352
DS21552
0010h
0019h
0005h
0003h
0004h
0002h
Note: When polling any single port on the DS21Q55,
the device ID returned will be the DS2155 device ID.
30.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers, the boundary scan register and the bypass register.
An optional test register, the identification register, has been included with the DS21Q55 design. It is
used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
30.4 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital
I/O cells. It is n bits in length. See Table 30-D for cell bit locations and definitions.
30.5 Bypass Register
This is a single one-bit shift register used with the BYPASS, CLAMP, and HIGH-Z instructions that
provides a short path between JTDI and JTDO.
30.6 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register
is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
See Table 30-B and Table 30-C for more information on bit usage.
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