MX86250 Datasheet, PDF (20/25 Pages) List of Unclassifed Manufacturers – THE ADVANCED 64-BIT WINDOWS-95 AND DIRECTDRAW ACCELERATOR

INDEX
MX86250
Media Port and Feature Connector Related Interface Pins:(continued)
Pin Name
BLANKB
HSYNCB
VSYNCB
L4VS
SCK
Pin No. Type Description
154 IO This is a multi-function pin.
For 8-bit Feature Connector or VAFC, when EVIDEO# is high, the internal BLANK#
signal is used to control RAMDAC display. In this case,it is an output pin if the
BLANK control for DPMS, which is defined in bit [1:0] of register 3?5/26, is not set
to 11. Otherwise, it will be tri-stated. When EVIDEO# is set to 0, it's an input from
Feature Connector. GUI uses it to control RAMDAC display.
For VMI or SAA7110, it’s the HREF input. And for CL480 it's the HSYNC# input.
In either case, it indicates that video data of a scanline is coming in.
155 TO It's the HSYNC# output pin, which is the horizontal sync to analog monitor. For 8-
bit Feature Connector or VAFC, it is enabled when EVIDEO# is high and HSYNC
control for DPMS,
which is defined in bit [3:2] of register 3?5/26, is set to value other than 11.
Otherwise, it is tri-stated. But if either SAA7110 or CL480 is select, it is enabled
also.
156 TO It's the VSYNC# output pin, which is the vertical sync to analog monitor. For 8-bit
Feature Connector or VAFC, it is enabled when EVIDEO# is high and VSYNC
control for DPMS, which is defined in bit [5:4] of register 3?5/26, is set to value
other than 11. Otherwise, it is tri-stated. But if either SAA7110 or CL480 is select,
it is enabled also.
198 IO If external VCG is selected, this pin is used as one of the MCLK select output,
MCSEL1. MCSEL[2:0] is used to select MCLK frequency from external VCG. If
internal VCG is used, it is an input pin for video interface. It’s the VREF for VMI, VS
for SAA7110 and VSYNC# for CL480. Either one indicates that it’s the frame start
of input video data.
5
IO It's the I²CCLK input/output pin for both SAA7110 interface or DDC2 monitor
control. As an input, the I²C CLK value can be monitored by reading bit 2 of the
memory-mapped register port at offset 31C or bit 2 of the I/O register at 3?5/50.To
generate clock pulses, software can just program either bit 0 of the above memory-
mapped register or bit 5 of the IO register at 3C4/1E. If 0 is programmed, this pin is
pulled low. If 1 is programmed, this pin is tri-stated. With the external pull-up, it
makes I2 CCLK go to high state. In this way, clock pulses are generated.
P/N:PM0387
REV. 1.1, JUL 26, 1996
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