TSL202R Datasheet, PDF (2/9 Pages) List of Unclassifed Manufacturers – 128 *1 LINEAR SENSOR ARRAY

TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032B – AUGUST 2002
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
AO1
4
Analog output of section 1
AO2
8
Analog output of section 2
CLK
3
Clock. Clk controls charge transfer, pixel output, and reset.
GND
5,12 Ground (substrate). All voltages are referenced to GND.
NC
7, 9, 11, 14 No internal connection
SI1
2
Serial input (section 1). SI1 defines the start of the data-out sequence.
SI2
10
Serial input (section 2). SI2 defines the start of the data-out sequence.
SO1
13
Serial output (section 1). SO1 provides a signal to drive the SI2 input.
SO2
6
Serial output (section 2). SO2 provides a signal to drive the SI input of another device for
cascading or as an end-of-data indication.
V_DD
1
Supply voltage. Supply voltage for both analog and digital circuitry.
Detailed Description
The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.
The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)^†. As the SI pulse
is clocked through the 128-bit shift register, the charge on the sampling capacitor of each pixel is sequentially
connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes
low, the pixel integrator is reset. On the 129th clock rising edge, the SI pulse is clocked out of the shift register
and the output assumes a high-impedance state. Note that this 129th clock pulse is required to terminate the
output of the 128th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented
as early as the 130th clock pulse, thereby initiating another pixel output cycle.
The voltage developed at analog output (AO) is given by:
where:
V_out
V_drk
R_e
E_e
t_int
V_out = V_drk + (R_e) (E_e) (t_int)
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(µJ/cm²)
is the incident irradiance in µW/cm²
is integration time in seconds
AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is
nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device
is not in the output phase, AO is in a high impedance state.
A 0.1 µF bypass capacitor should be connected between V_DD and ground as close as possible to the device.
† _{For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.}
Copyright E 2002, TAOS Inc.
2
t
www.taosinc.com
The LUMENOLOGYr Company
t