TM54S816T-6G Datasheet, PDF (2/7 Pages) List of Unclassifed Manufacturers – SPECIFICATION FOR APPROVAL

TMC
TM54S816T-6G
Description
The TM54S816T is organized as 4-bank x 2097152-word x 16-bit(8Mx16),
fabricated with high performance CMOS technology. Synchronous design
allows precise cycle control with the use of system clock I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device to be useful
for a variety of high bandwidth, high performance memory system applications.
Features
„ Package: 400-mil 54-pin TSOP(II)
„ JEDEC PC133/PC100 compatible
„ Single 3.3V Power Supply
„ LVTTL Signal Compatible
„ Programmable
- CAS Latency (3 or 2 clocks)
- Burst Length (1,2,4, 8 & full page)
- Burst type (Sequential & Interleave)
„
„
„ Auto and Self Refresh
„ 64ms refresh period (4K Refresh)
„
organization
„
„ Pin36 and 40 are “No Connected”
„ Fully synchronous operation referenced
to clock rising edge
Frequency vs. AC Parameter
- 6G - 7G - 75G Unit
f_CK3 ^{Max. operating frequency @CL=3}
166 143
133
Mhz
f_CK2 ^{Max. operating frequency @CL=2}
133 133
100
Mhz
t_CK3 ^{Min. clock cycle time @CL=3}
6.0 7.0
7.5
ns
t_AC3 ^{Max. access time from CLK @CL=3 5.0}
5.4
5.4
ns
t_CK2 ^{Min. clock cycle time @CL=2}
7.5 7.5
10
ns
t_AC2 ^{Max. access time from CLK @CL=2 5.4}
5.4
6.0
ns
t_rcd ^{Min. row to column delay}
15
18
18
ns
For reference only.
2
TMC Rev: 1.1