TC3000 Datasheet, PDF (2/2 Pages) List of Unclassifed Manufacturers – Turbo Product Code decoders

Flexibility
TC3000 family offers 3 levels of flexibility :
TC3000 family member
9 BCH t=2 code support (YES/NO)
9 Choice on bitrate
9 VHDL generic parameters Maximum row code length
9 Maximum column code length
before synthesis
9 Input Quantization width
9 1 or 2 input buffers
On-the fly parameters
9 Row code
9 Column code
from block to block
9 Shortening values
9 Max. number of iterations
9 Stopping feature enabled
FEC performance
Very high FEC performance are obtained for various block sizes and coding rates. The FEC behaviour
of the “BCH t=2” codes makes them particularly attractive for quasi-error free applications.
Ö Gaussian channel and QPSK modulation. Results given with 5 iterations.
Product Code
Rate Eb/N0 @BER=10^-5 Eb/N0 @BER=10^-8
(32,26) x (32,26)
0.660
2.9 dB
3.6 dB
(32,21) x (32,21)
0.431
2.4 dB
N.A.
(64,57) x (64,57)
0.793
3.2 dB
3.6 dB
(64,51) x (64,51)
0.635
2.6 dB
2.9 dB
(128,120) x (128,120) 0.879
3.8 dB
4.2 dB
(128,113) x (128,113) 0.779
3.3 dB
3.4 dB
(256,247) x (256,247) 0.931
4.5 dB
4.8 dB
(256,239) x (256,239) 0.872
4.0 dB
N.A.
Block Diagram
Input
Interface
DCK
DBLK
DEN
D[D_WIDTH-1:0]
DRDY
Input
module
Input
Buffer #1
Input
Buffer #0
Decoder
module
Output
Buffer
Output
module
QCK
QBLK
QEN
Q
QRDY
Output
Interface
Global
Signals
CK
RSTB
MSELECT
TC3000
Dedicated
Configuration
I/Os
Configuration module
Microcontroller
Interface
Implementation results
Product
TC3011
TC3014
TC3022
Codes supported
Hamming BCH t=2
9
9
99
Generic parameter setting
Implementation results
Row max. Column Data bank LE ESB APEX20K Fmax Typical Bitrate
length max. length _{width swap}
device
MHz @(64,57)², 5 iterations
64
64
4 NO 2025 22 200 C7 82
8 Mbits/s
64
64
4 NO 6926 36 200 C7 72
25 Mbits/s
128
128
4 NO 8115 88 400 C7 67
23.5 Mbits/s
64
64
4 NO 8932 24 400 C7 79
14 Mbits/s
This document contains preliminary information. Information is subject to change without notice.
TC3000 is covered by several patents.