S24VP04 Datasheet, PDF (2/12 Pages) List of Unclassifed Manufacturers – 4K Serial E2PROM with a Precision Low-VCC Lockout Circuit

S24VP04
PIN CONFIGURATIONS
Plastic Dual-in-line
“P” Package
Address Inputs A0, A1, A2- Device Address Inputs
These inputs are unused by the S24VP04; however, to
ensure proper operation they should be left unconnected
or tied to ground. The should not be tied high.
A0 ₁
A1 ₂
A2 ₃
GND ₄
8 V_CC
7 DC
6 SCL
5 _SDA
JEDEC Small Outline
“S” Package
A0 1
A1 2
A2 3
GND ⁴
8 V_CC
7 DC
6 SCL
5 SDA
2008 ILL1 1.2
PIN NAMES
A0, A1,A2
SDA
SCL
DC
GND
V_CC
Address Inputs
Serial Data I/O
Serial Clock Input
Don’t Care
Ground
Supply Voltage
PIN DESCRIPTIONS
Serial Clock (SCL) - The SCL input is used to clock data
into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA) - The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
outputs.
ENDURANCE AND DATA RETENTION
The S24VP04 is designed for applications requiring
1,000,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 1,000,000
erase/write cycles.
DEVICE OPERATION
APPLICATIONS
The S24VP04 was designed specifically for applications
where the integrity of the stored data is paramount. In
recent years, as the operating voltage range of serial
E²PROMs has widened, most semiconductor manufac-
turers have arbitrarily eliminated their V_CC sense circuits.
The S24VP04 will protect your data by guaranteeing write
lockout below the selected V_CC Lockout voltage.
V_CC Lockout
The S24VP04 has an on-board precision V_CC sense
circuit. Whenever V_CC is below V_LOCK, the S24VP04 will
disable the internal write circuitry. The V_CC lockout circuit
will ensure a higher level of data integrity than can be
expected from industry standard devices that have either
a very loose specification or no V_CC lockout specification.
During a power-on sequence all writes will be inhibited
below the V_LOCK level and will continue to be held in a write
inhibit state for approximately 200ms after V_CC reaches,
then stays at or above V_LOCK. The 200ms delay provides
a buffer space for the microcontroller to complete its
power-on initialization routines (reading is OK) while still
protecting against inadvertent writes.
During a power-down sequence initiation of writes will be
inhibited whenever V_CC falls below V_LOCK. This will guard
against the system’s microcontroller performing an inad-
vertent write within the ‘danger zone’. (see AN001)
2008 1.4 5/15/98
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