OZ965 Datasheet, PDF (2/7 Pages) List of Unclassifed Manufacturers – High-Efficiency Inverter Controller

OZ965
FUNCTIONAL BLOCK
DIAGRAM
Refer to the functional block diagram in Figure 2,
below, and the Pin Description Table on page 3.
Power is transferred to the transformer primary
by the N-MOSFET, driven by the MOSFET gate
driver out of pin NDR. The P-MOSFET resets the
primary field, driven by pin PDR. The usual
design results in approximately 50% duty cycle at
full lamp intensity. Terminating the NDR signal
earlier than the full brightness lamp pulse width
performs lamp dimming, using the analog
dimming. The voltages on pins HCLMP and
LCLMP set a threshold voltage for the ramp
comparator setting the maximum duty cycle for
NDR.
A pulse generator circuit creates the clock signal
with the frequency determined by an external,
constant current setting resistor (RT) and timing
capacitor (CT).
The “soft-start” circuit ensures a reliable and long
lamp life starting condition.
REF
1
2.50V
IBIAS
&
POFF
REFERENCE
“Soft start” gradually increases the energy
delivered to the secondary.
When the OZ965 is enabled at pin ENA, the
capacitor on pin SST determines the duration of
the “soft-start” period, gradually increasing the
NDR pulse width to the regulated brightness. The
“soft-start” period provides sufficient time for the
lamp to ignite.
For system reliability there are several circuit
protections provided. To ensure a controlled
output, the secondary current is monitored on pin
FB and is compared to a reference voltage on pin
ADJ. The NDR signal is shortened or lengthened
dependent upon this feedback. Protection is
provided by the resultant signal, CMP, monitoring
for a lamp removal condition. Short circuit
protection is provided at pin SCP. The OPS
signal selects either HCLMP or LCLMP providing
current protection against an “Open Lamp”
condition at start-up. The OPS signal also allows
adjustment to different transformer models.
To reduce power dissipation, the switch
(MOSFET) drive signals are “break-before-make”
with a short, fixed off time between activation of
NDR or PDR.
Vdd
16
HCLMP
2
LCLMP
3
SCP
4
Vset
+
Vmax=2.6V-Vset
-
Vmax
V
V>Vmax -- -> Vmax
Vmin<V<Vmax ->V
V<Vmin -- ->Vmin
Vmin
(fix value)
+
RAMP
COMP.
-
RT
15
+
2.5V
COMP
-
PULSE GEN
+
CT
COMP
0.5V
14
-
ADJ
5
+
EA
-
FB
6
CMP
7
GND
8
R4
70k
2.5V
R5
630k
+
COMP
-
Note:
OVP – Over Voltage Protection
SCP – Short-Circuit Protection
UVL – Under Voltage Lockout
SS1
t1
(slow start)
RESET
UVLO
+
0.6V
COMP
LAMP
OPS
Vdd
- ^ON/OFF
13
UNDER VOLTAGE
LOCKOUT
ENABLE
ZVS
CONTROLLER
Pgate
+
COMP
-
ENA
R1
300k
12
ACTIVE
"HIGH"
1.5V
PDRV
PDR
11
OLPROT
PROTECTION
Ngate
NDRV
NDR
10
I=12uA
SS2
I=2.5uA
V_SS2
t1+t2
(slow start)
SS1
SST
9
R2
4K
POFF
MN1
Figure 2. Functional Block Diagram
OZ965-SF-3.0
Page 2