ICS87354I Datasheet, PDF (2/10 Pages) List of Unclassifed Manufacturers – -2.5V/ 3.3V LVPECL CLOCK GENERATOR

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS87354I
÷4/÷5 DIFFERENTIAL-TO-2.5V/3.3V
LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
CLK
Input Pulldown Non-inverting differential clock input.
2
nCLK
Input
Pullup Inverting differential clock input.
Master reset. When LOW, outputs are enabled. When HIGH,
3
MR
Input Pulldown divider is reset forcing Q output LOW and nQ output HIGH.
LVCMOS / LVTTL interface levels.
4
F_SEL
Input
Pulldown
Selects divider value for Q, nQ outputs as described in table 3.
LVCMOS / LVTTL interface levels.
5
V_EE
Power
6, 7
Q, nQ
Output
Negative supply pin.
Differential output pair. LVPECL interface levels.
8
V_CC
Power
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
TABLE 3. FUNCTION TABLE
MR F_SEL
Divide Value
1
X
Reset: Q output low, nQ output high
0
0
÷4
0
1
÷5
CLK
MR
Q
FIGURE 1. TIMING DIAGRAM
87354AMI
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 27, 2003