GD90590 Datasheet, PDF (2/5 Pages) List of Unclassifed Manufacturers – HIGH SPEED CLOCK WYNTHESIZER EVALUATION BOARD

Functional Details
General
Mode Control
The GD16590 offers a fully integrated PLL including on-chip
VCO, and with inputs for use of an external VCXO. Three
selectable differential reference clock inputs and six subdivided
differential oscillator outputs are available on the GD90590
evaluation board.
Reference Clock inputs
The three differential reference clock inputs (J3/J4, J5/J6 and
J7/J8) are AC coupled LVPECL inputs, internally terminated in
the GD16590 device. Selection of the active input is done from
DIP switch (S1).
Clock Output Signals
The subdivided clock outputs are generated as differential
LVPECL signals. Each signal is DC terminated on the board via
120 W to ground. The signals are AC coupled out of the board
to the SMA connectors (J10…J21). The signals can be DC cou-
pled to the load if the internal termination resistors are removed
and the coupling capacitors are replaced by 0 W resistors. Each
of the six outputs can be switched off by pulling the correspond-
ing LVT select signal (OUTENAx) to ground. The output select
signals are controlled by DIP switch (S2).
Important note: Failure to terminate an active (enabled) output
may cause degradation of the device performance.
The GD16590 compares selected reference clock input signal
with the selected subdivided oscillator frequency. The charge
pump output OCHP reflects the phase relationship between the
compared signals. The frequency of the charge pump output
(the error signal frequency) follows the reference clock fre-
quency directly. This means the gain of the PLL loop is directly
proportional with the input reference clock frequency. Hence
you should expect the jitter performance of the application to be
dependent on the reference clock frequency in use.
General Purpose Clock Divider Operation
In addition to the frequency limited clean-up operation the
GD16590 can be used as a general purpose high speed clock
divider. The clock input is J1(/J2) as described above, and one
or more outputs will provide a binary divided clock output in the
terminals J10…J21, depending on the output enable signal set-
ting in DIP switch (S2).
Power Supply
The GD90590 evaluation board may be powered from an un-
regulated power supply, delivering +6 V, 400 mA minimum.
A stabilised 3.3 V supply for the GD16590 is generated locally
on the board.
Loop Filter
The PLL loop filter is composed of the components R49/C24.
For a specific application the mounted default values may need
to be changed for optimum performance since the jitter perfor-
mance of the PLL depends on the input frequency. There is
space for an additional loop filter capacitor (C25). When the in-
ternal VCO is used, the loop current flows from OCHP via R46
to the VCTL input.
On-board VCXO
The GD90590 evaluation board comprises a VCXO mounted in
position U4. This VCXO may be used as an alternative to the
VCO integrated in the GD16590. When the VCXO is used the
control loop for the PLL comprises an active loop filter com-
posed of the operations amplifier (U3 - LMV358M). The filter,
which has a DC adjustment of the working point in P3, controls
the VCXO (U4 - VF900409). The VCXO output is AC coupled
via C45 to the VCXO input terminal of the GD16590. The VCXO
input is a differential input to the GD16590. Hence the trigger
point of the device, i.e. the input duty cycle can be adjusted by
P1.
External Oscillator
An alternative to the on-chip VCO and the on-board VCXO is to
add an external clock signal. Use J1 (VCXO) for single ended
input or J1/J2 (VCXO/DCCAL) for differential input. The external
clock is terminated in R13/R18. Remove capacitors C40 and
C45 to avoid stub reflections and conflicts with U4.
When using single ended input duty cycle can be adjusted by
means of P1, if R5 = 470 W is mounted.
Data Sheet Rev.: 04
GD90590
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