DDU8C3 Datasheet, PDF (2/4 Pages) Data Delay Devices, Inc. – 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE

DDU8C3
APPLICATION NOTES
HIGH FREQUENCY RESPONSE
The DDU8C3 tolerances are guaranteed for input
pulse widths and periods greater than those
specified in the test conditions. Although the
device will function properly for pulse widths as
small as 40% of the total delay and periods as
small as 80% of the total delay (for a symmetric
input), the delays may deviate from their values at
low frequency. However, for a given input
condition, the deviation will be repeatable from
pulse to pulse. Contact technical support at Data
Delay Devices if your application requires device
testing at a specific input condition.
POWER SUPPLY BYPASSING
The DDU8C3 relies on a stable power supply to
produce repeatable delays within the stated
tolerances. A 0.1uf capacitor from VDD to GND,
located as close as possible to the VDD pin, is
recommended. A wide VDD trace and a clean
ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
V_DD
V_IN
T_STRG
T_LEAD
-0.3
7.0
V
-0.3
V_DD+0.3
V
-55
150
C
300
C
10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.00V to 3.60V)
PARAMETER
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Current
SYMBOL
V_OH
V_OL
I_OH
I_OL
V_IH
V_IL
I_IH
MIN
3.00
2.50
TYP
3.20
0.10
MAX
0.30
-24.0
24.0
0.80
0.10
UNITS
V
V
mA
mA
V
V
µA
NOTES
V_DD = 3.3, I_OH = MAX
V_IH = MIN, V_IL = MAX
V_DD = 3.3, I_OL = MAX
V_IH = MIN, V_IL = MAX
V_DD = 3.3
Doc #00115
DATA DELAY DEVICES, INC.
2
5/19/00
Tel: [phone] Fax: [phone] www.datadelay.com