CY100 Datasheet, PDF (2/4 Pages) List of Unclassifed Manufacturers – Companion IC with 5 V ADC

preliminary
GENERAL DESCRIPTION
The CY100 is designed to assist a low voltage micro-
controller in automotive applications. The eight channel
10 bit analog-to-digital converter ADC operates half-auto-
matically with 5 V-inputs. Because of the possibility of slew
rate limitation, the ISO interface can operate both in BSS
and LIN applications. Two signal stages with diagnosis can
be used to control small signal loads like light emitting
diodes ( LEDs ). With the SPI interface the controller can
communicate without real time conditions up to 2 Mbaud.
MAXIMUM RATINGS
Parameter
Maximum Voltage, RT
Maximum Voltage, UBat, UB_REF
Maximum Voltage, A1, A2
Maximum Voltage, VDD5, VDD5A, AREF
Maximum Voltage, VDDIO
Maximum Voltage, AN_INx, CLK, E1, E2,
RST, SCK, SI, SS, TX
Maximum Voltage, INT, RX, SO
Frequency operating range
Maximum SPI transfer rate
Operating temperature Tj
Thermal resistance
ESD HBM, MIL883D 3015 100pF / 1.5kΩ
A1, A2, RT
All other pins
Min Max Unit
-15 60
V
-2
60
V
-0.6 60
V
-0.3 6
V
-0.3 4
V
-0.3 UVDD5 V
+ 0.3
-0.3 UVDDIO
V
+ 0.3
2.5 12 MHz
2 MBd
-40 150 °C
60 K/W
- 4 + 4 kV
- 2 + 2 kV
A / D CONVERTER ( ADC )
The CY100 uses an 10 Bit SAR ( successive
approximation register ) Converter with S & H ( sample
and hold ) element. The total error ( gain, offset, non-
linearity ) is less than 2 LSB and less than 4 LSB near
ground or AREF. The CY100 has an internal offset
compensation algorithmus. The conversion and sample time
for each channel is faster than 125 us. The ADC is muxed
to 8 external input channels except channel 5, which is
additional multiplexed with the internal channel for the
CY100 offset compensation on chip.
So a converting time of 1 ms of channel 0 to 4 and 6 to
7 can reached, whereas channel 5 can be converted every
2 ms. All 8 channels are running in timed mode without
jitter.
The input voltage range is 0 V .. 5.5 V. The input pins
AN_INx are clamped to VDD5 and GND by an ESD
protection diode. The ADC has a separate reference input
pin AREF.
After conversion of all 8 channels the results are storaged
in the result RAM. After ending the conversion of channel 7
the output INT becomes active ( low ). This output can be
used to trigger a microcontroller with interrupt or DMA
request.
Parameter
Input range
Switched capacitance
Resolution for the input range
Conversion time for each channel
( f=2,5 MHz )
Maximum sample rate
AREF = 5 V :
Resolution, 0.1 V < AN_INx < 4.9 V
Resolution, AN_INx ≤ 100 mV
Resolution, AN_INx ≥ 4.9 V
Min Max Unit
-0.3 UVDD5A
V
+ 0.3
20 pF
10 Bit
122 µs
1 kHz
± 2 LSB
± 4 ^LSB
± 4 ^LSB
VD D5
MUX
AN_IN0
GN DA
VDD5
AN_IN3
Rin
Cmax
GND A
Rmux
Rmux
Rmux
Rmux
Rmux
Rmux
Rmux
Rmux
AREF
offset
channel
Rmux
TESTM3
T_{Testm 3}
R
DSon
GND A
offset
reference
for compensation
S&H
Cs
ADC (10 Bit; SAR)
01 1 01 1 0101
digital offset
compensation
result register
RAM
Bank0 Bank1
INT
Control
f_cycle
Divider 2
(2500, 3000,
5000 or 6000)
internal bus
ADC - SPI transfer
register (BIOR)
f_CCLK
(=2.5MHz or3MHz)
Divider 1
(1,2,3 or 4)
SPI
CLK
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Robert Bosch GmbH retains the sole powers of distribution, such as reproduction, copying and distribution.
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