BCM8212 Datasheet, PDF (2/2 Pages) Broadcom Corporation. – TRANSCEIVER WITH INTERNAL LOOP TIMING AND PHASE DETECTOR

BCM8212 OVERVIEW
PHDCKP
PHDCKN
RESETB
CLK16IP
CLK16IN
DI0
DI15
CKSEL
RTSYNC
REFCKP
REFCKN
REF 155EN
DOSQ
RCK16SQ
RDINP0
RDINN0
RDINP1
RDINN1
SELRD1
LOSIB
VCN_CDR
VCP_CDR
RCK1SEL
REFCKENB
LPBKFB
TSEL
LPBKSB
A
FIFO
Control
Phase
Detector
Write
Pointer
Charge
Pump
Divide-by-2
Output
Retime
Read
M
B
Pointer
A
M
U
X
2.488 GHz PLL
F
M
U
X
M
U
X
M
B
Divide-by-16
LVPECL REF
L
K
E
CDR
J
F
K
Loop-
back
Logic
A
L
F
M
Divide-by-16
U
X
J
M
Divide-by-2
U
X
Loss Detect
PD OUT
PD LKDT
OVFB
TCK320
TXDP
TXDN
TXCKP
TXCKN
TCK16OP
TCK16ON
TXLKDT
IOVREF
DO0
DO15
RCK16OP0
RCK16ON0
RCK16OP1
RCK16ON1
RXLKDT
LOSB
The BCM8212 SONET/SDH transceiver is a fully integrated
serialization/deserialization SONET OC-48 (2.488 Gbps) interface
device with an integrated Clock Multiplication Unit (CMU) and an
integrated Clock and Data Recovery (CDR) circuit. On-chip clock
synthesis is performed by the high- frequency and low-jitter, phase-
locked loop on the BCM8212 transceiver chip, allowing the use of a
slower 77.76/155.52-MHz external transmit clock reference.
Dual RX and TX 2.488 Gbps interfaces support dual-fiber ring
architectures. Clock recovery is performed on the device by
synchronizing its on-chip VCO directly to the incoming data stream. The
low-jitter, LVPECL interface guarantees compliance with the bit error
rate requirements of the Telcordia GR-253-CORE, ANSI, and ITU-T
standards. The BCM8212 is packaged in a 23 x 23 x 1.53 mm, 208-pin
BGA.
The BCM8212 operates in a 2.5/3.3V configuration. The core and CML
I/Os operate at 2.5V. The LVPECL I/Os operate at 3.3V.
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BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
8212-PB05-R
04/15/03
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