BCM8021 Datasheet, PDF (2/2 Pages) Broadcom Corporation. – 4 CHANNEL MULTIRATE 1.0-3.2 GBPS TRANSCEIVER WITH HIGH SPEED REDUNDANCY

OVERVIEW
10G XAUI_0
Channel_0 (1–3.2G)
Channel_1 (1–3.2G)
Channel_2 (1–3.2G)
Channel_3 (1–3.2G)
10G XAUI_1
Channel_4 (1–3.2G)
Channel_5 (1–3.2G)
Channel_6 (1–3.2G)
Channel_7 (1–3.2G)
Bus
Mux
MDIO/MDC
MGMT
Required: 1.2V, 2.5V,
I/O options: 1.5V, 1.8V, 2.5V, or 3.3V
10G XGMII
Channel_0 (TBI, RTBI)
Channel_1 (TBI, RTBI)
Channel_2 (TBI, RTBI)
Channel_3 (TBI, RTBI)
(Control/Clocking)
PBERT
BCM8021
The BCM8021 device integrates 4 independent serializer/deserializer
(SerDes) channels leveraging Broadcom’s high-performance mixed-
signal design experience along with advanced 0.13-µ CMOS process
technology. Combine this with a robust architecture offering the highest
degree of flexibility and the result is a highly programmable, lowest
power SerDes solution for network line-card and backplane applications.
An internal switch connects the parallel and serial ports to enable fully
redundant operation. The switch enables an active serial link to be
switched to the parallel interface, while a protection serial link can be
continuously monitored to insure its condition. In the event of a failure
on the active link, the protection link can be instantly switched over
through external control to the parallel interface.
On the parallel side of the device, transmitters and receivers interface
with either 5-bit (RTBI) or 10-bit (TBI) wide data on each channel, or
can be configured to interface to 32-bit wide data (XGMII) along with
the clock and control signals. The low-speed I/O supports HSTL (1.5V
or 1.8V) or SSTL_2 (2.5V) interfaces.
On the serial side of the device, transmitters and receivers support serial
transmission rates ranging from 1 Gbps to 3.2 Gbps. An on-chip phase
lock loop (PLL) synthesizes the supplied reference clock to support the
desired transmit rate, while vlock and data recovery (CDR) units recover
the receive rate clock for timing. The interface can support single-
channel (octal) or quad (XAUI) differential CML I/O.
For high-speed serial copper connections, the device incorporates both
Tx pre-emphasis on the transmit channels and Rx equalization on the
receive channels. Transmit pre-emphasis is programmable to improve
the overall cable reach and compensate for electrical imperfections
associated with traces and connectors. Rx equalization provides optimal
performance over a variety of receive interfaces.
Highly programmable test capabilities exist within the device to support
high-speed and low-speed loopback using generators/checkers that
support PRBS 27 to 231 patterns along with IEEE802.3ae defined test
patterns. A complete evaluation kit, including an evaluation board,
related software, and documentation is available upon request.
Applications
• 1-Gigabit Ethernet and 10-Gigabit Ethernet LAN, MAN, WAN
switches and routers
• 1×, 2×, or 10-Gbps Fibre Channel SONET network cards
• Advanced Test Equipment (ATE)
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8021-PB02-R
04/14/04
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