BCM4500 Datasheet, PDF (2/2 Pages) Broadcom Corporation. – ADVANCED MODULATION SATELLITE RECEIVER

BCM4500 OVERVIEW
Functional Block Diagram
RA_I
RA_Q
AGC_CTRL
DISEQC
7
A/D
7
A/D
Phase/
Frequency
Recovery
Variable
Rate
Demod
Nyquist
a = 0.20, 0.35
Nyquist
a = 0.20, 0.35
12-tap
FFE
Acquisition/Tracking Loops
and Clock Generation
DiSEqC 2.0
Block
Header
Processor
Viterbi
Decoder
Iterative
Decoder
Sync &
Deinter-
leaver
Outer
RS
Decoder
t=10
M
U
X
RS
Decoder
DATA[7:0]
CLK
VALID
SYNC
ERR
Acquisition
Microcontroller
MBus/SPI
Interface
MICRO[4:0]
The BCM4500 brings a new level of performance to the satellite
television industry with the introduction of an integrated
advanced modulation receiver and turbo FEC decoder. This
breakthrough design provides 50% more throughput in the same
satellite bandwidth at standard QPSK operating points while
simultaneously improving BER performance beyond existing
levels. A high performance turbo FEC code is implemented
with all required on-chip RAM to move system operating points
near the theoretical capacity limits. A Reed-Solomon outer code
is also used to drive the BER beyond typical satellite 10E-11
limits.
The BCM4500 is a single-chip digital satellite receiver
supporting BPSK, QPSK, 8PSK and 16QAM modulations with
iteratively (turbo) decoded error correction coding. It represents
an industry milestone in terms of satellite system throughput and
operating points. The BCM4500 also receives DVB,
DIRECTV^® and Digicipher^TM II (DCII), QPSK signals to
support legacy system operation.
The BCM4500 contains dual 7-bit A/D converters, an
all-digital variable rate BPSK/QPSK/8PSK/16QAM receiver, an
advanced modulation turbo FEC decoder, and a
DVB/DIRECTV/DCII compliant FEC decoder. All required
RAM is integrated and all required clocks are generated on-chip
from a single reference crystal. Baseband IQ analog waveforms
are sampled by the integrated 7-bit A/D converters, resampled
by integrated interpolative digital filter banks, and filtered by
dual square-root Nyquist filters. Optimized soft decisions are
then fed into either a DVB/DIRECTV/DCII-compliant FEC
decoder, or an advanced modulation turbo decoder. The final
error-corrected output is delivered in MPEG-2 or DIRECTV
transport format. The output clock is generated by an on-chip
PLL for low-jitter operation and glueless integration with
Broadcom’s BCM7020 HD graphics and video subsystem.
The BCM4500 also features a simplified user interface
employing an on-chip microcontroller for all system
configuration, acquisition, control, and monitoring functions.
The host interface to the device is via a simplified, high-level
application programmer interface (API). The chip also contains
an integrated DiSEqC^TM 2.0 controller with integrated voltage
regulator for two-way communication with LNBs. An on-chip
BERT is provided to simplify system test and manufacturing.
Broadcom^®, the Pulse logo^® and Connecting everything^® are trademarks of
Broadcom Corporation and/or its subsidiaries in the United States and certain other countries.
Digicipher^TM is a trademark of General Instrument (now Motorola).
DIRECTV^® is a registered trademark of DIRECTV, INC., a unit of Hughes Electronics Corporation.
DiSEqC^TM is a trademark of EUTELSAT. All other trademarks are the property of their respective owners.
®
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2003 by BROADCOM CORPORATION. All rights reserved.
4500-PB05-R-06.13.03
Phone: [phone]
FAX: [phone]
Email: [e-mail]
Web: www.broadcom.com